A wireless communication apparatus includes: a processor that performs distortion compensation on a transmission signal by using a distortion compensation coefficient; an amplifying unit that amplifies the transmission signal; and a feedback path that feeds back a feedback signal to the processor. The processor executes a process including: acquiring, from a transmission signal at a first timing and feedback signals at a second timing that is before the first timing and at a third timing that is after the first timing, instantaneous delay associated with propagation delay of the feedback signals in the feedback path; calculating a mean value of the instantaneous delay acquired in a predetermined time period; adding delay associated with the calculated mean value to the transmission signal; and updating the distortion compensation coefficient by using the transmission signal to which the delay is added and the feedback signal.

According to certain embodiments, a method (500) by a wireless device (110) includes receiving information relating to a Narrowband Secondary Synchronization Signal (NSSS) transmit diversity scheme. The information indicates a number of NSSS occasions that use different NSSS transmit diversity configurations. Based on the NSSS transmit diversity scheme, at least one measurement is performed across NSSS occasions.

A system comprising transmission circuitry to communicate first data to receiver circuitry over a serial communication link during an active state of the serial communication link; and power adjustment circuitry to adjust a power level of the transmission circuitry responsive to a request based on at least one margin measurement performed by the receiver circuitry on the first data, wherein the transmission circuitry is to communicate second data using the adjusted power level over the serial communication link.

Embodiments disclosed herein relate to improving a power output of a transmitter of an electronic device. To do so, the transmitter may include signal selection circuitry to adjust a sign selection signal to accurately transition between polarities of a quadrature (e.g., I or Q) component signal stored in or for which an indication is stored in a storage cell of a radio frequency digital-to-analog converter. The sign selection signal may generate a separate adjusted sign selection signal for each polarity of each quadrature component signal such that a transition of the selection signal between a first value and a second value (e.g., logic high and low) occurs when the respective quadrature (e.g., +/− and I/Q component signal is a logic low. In this way, the signal selection circuitry reduces an error pulse in the output of the transmitter.

A data transmitter includes a transmitting circuit configured to transmit data, the data including alternating odd-numbered data and even-numbered data. The transmitting circuit includes a first flip flop configured to receive the odd-numbered data and generate retimed odd-numbered data, and a second flip flop configured to receive the even-numbered data and generate retimed even-numbered data. The data transmitter includes a clock transmitting circuit configured to supply a clock signal to the transmitting circuit, the clock transmitting circuit including a clock driver configured to transmit the clock signal to a receiver that receives the data.

Digital n-state switching devices are characterized by n-state switching tables with n greater than 4. N-state switching tables are transformed by a Finite Lab-transform (FLT) into an FLTed n-state switching table. Memory devices, processors and combinational circuits with inputs and an output are characterized by an FLTed n-state switching table and perform switching operations between physical states in accordance with an FLTed n-state switching table. The devices characterized by FLTed n-state switching tables are applied in cryptographic devices. The cryptographic devices perform standard cryptographic operations or methods that are modified in accordance with an FLT. One or more standard cryptographic methods are specified in Federal Information Processing Standard (FIPS) Publications. Security is improved by at least a factor n.sup.2.

A memory controller having a data receiver to sample data at a sample timing using a strobe signal, wherein the data and the strobe signal are sent by a memory device in connection with a read operation initiated by the memory controller, and a strobe receiver to receive the strobe signal, wherein a phase of the strobe signal has a drift relative to a reference by an amount. The memory controller further having a monitoring circuit to monitor the strobe signal and determine the amount of the drift, and an adjustment circuit to update the sample timing of the data receiver based on the amount of drift determined by the monitoring signal.

A channel between quantum controller modules (e.g., pulse processors) is operable to communicate high speed data required for processing qubit states that may be distributed across a quantum computer. The latency of the communication channel is deterministic and controllable according to a system clock domain.

The present invention discloses an image data transmission apparatus. The lock confirmation circuit receives an original signal having an original pulse width from the image data reception apparatus to generate an output signal. The image data transmission circuit determines that the image data reception apparatus locks a transmission frequency when an output pulse width is larger than a pulse threshold value to perform a synchronous image data transmission. The lock confirmation circuit sets the output pulse width to be a lengthened pulse width when a difference between the original pulse width and the pulse threshold value is smaller than a predetermined value and the original pulse width is not smaller than the pulse threshold value. The lock confirmation circuit sets the output pulse width to be a shortened pulse width when the difference is smaller than the predetermined value and the original pulse width is smaller than the pulse threshold value.

In a case where signals branched from a single reference signal source are transmitted via a plurality of cables, a phase synchronization circuit can be used to stabilize a phase of a signal to be outputted from each cable. However, the phases of signal to be outputted from each cable is affected by combination of a length of each cable and an amount of delay caused by feedback control, so that phases of synchronization signals to be outputted from a plurality of transmission paths are not always the same as each other. In the present invention, since a frequency multiplier that multiplies a frequency of a signal outputted from each transmission path by an even number is provided for a phase synchronization circuit, the phases of the synchronization signals to be outputted from the transmission paths are aligned even when signals are branched from one reference signal.