A receiver includes an equalization circuit configured to output a data sample signal and an edge sample signal by sampling a data input signal according to clock signal, and to perform an equalization operation according to the data sample signal and the edge sample signal; and a clock gate circuit configured to select the clock signals from among a plurality of multi-phase clock signals according to a selection signal.

Systems for determining a phase of a device coupled to an electrical distribution system. The system includes a number of gateway devices configured to transmit a synchronization signal. The gateway device receives a node response message from a first node device that includes a duration value indicating a time between a receipt of the transmitted synchronization signal and a detected zero crossing. The gateway device compares the duration value against duration values received from node devices with a known phase connection and determines a phase of the first node device based on the comparison.

Systems for determining a phase of a device coupled to an electrical distribution system. The system includes a number of gateway devices configured to transmit a synchronization signal. The gateway device receives a node response message from a first node device that includes a duration value indicating a time between a receipt of the transmitted synchronization signal and a detected zero crossing. The gateway device compares the duration value against duration values received from node devices with a known phase connection and determines a phase of the first node device based on the comparison.

Systems and methods for dynamically adjusting a MAP advance time for a MAP message sent from a CCAP core to an RPD, based on a comparison of at least one measured latency value against at least one threshold.

Systems and methods for dynamically adjusting a MAP advance time for a MAP message sent from a CCAP core to an RPD, based on a comparison of at least one measured latency value against at least one threshold.

A process includes a port of a bridge providing a reference clock signal to a first end of an interconnect extending between the first port and a network interface controller. The reference clock signal propagates over the interconnect to provide, at a second end of the interconnect, a delayed reference clock signal at the network interface controller. Pursuant to the process, the bridge senses a timing of the delayed reference clock signal. The process includes communicating management traffic between a network interface of a baseboard management controller and the network interface controller via the interconnect. The communication of the management traffic includes the port, responsive to the sensing of the timing of the delayed reference clock signal, synchronizing communication of data with the first end of the interconnect to the delayed reference clock signal.

The technology disclosed herein facilitates the providing assurance for deletion of information from client systems using a distributed ledger network. One or more implementations disclosed herein provide using a user interface (UI) client to allow users to upload and delete information and a rest application programming interface (API) communicatively connected to the distributed ledger network logs the uploading and/or deletion of the information.

A network transceiver device is provided, including at least two variable gain amplifiers (VGAs), and at least two sets of analog digital converters (ADCs), each set including ADCs coupled to an output of one of the VGAs, the sets being arranged in VGA-specific channels. The device includes a plurality of feed-forward equalizers (FFEs), each FFE being coupled to receive an output of one of the ADCs in one of the VGA-specific channels. Each FFE is configured to adaptively equalize the output received from the ADCs utilizing a first equalization coefficient subset with coefficient values that are common to all FFEs, and a second equalization coefficient subset that is channel specific and that has a first set of coefficient values for a first VGA-specific channel and a second set of coefficient values for a second VGA-specific channel, the sets of coefficient values being computed independently.

A network transceiver device is provided, including at least two variable gain amplifiers (VGAs), and at least two sets of analog digital converters (ADCs), each set including ADCs coupled to an output of one of the VGAs, the sets being arranged in VGA-specific channels. The device includes a plurality of feed-forward equalizers (FFEs), each FFE being coupled to receive an output of one of the ADCs in one of the VGA-specific channels. Each FFE is configured to adaptively equalize the output received from the ADCs utilizing a first equalization coefficient subset with coefficient values that are common to all FFEs, and a second equalization coefficient subset that is channel specific and that has a first set of coefficient values for a first VGA-specific channel and a second set of coefficient values for a second VGA-specific channel, the sets of coefficient values being computed independently.

A process includes a port of a bridge providing a reference clock signal to a first end of an interconnect extending between the first port and a network interface controller. The reference clock signal propagates over the interconnect to provide, at a second end of the interconnect, a delayed reference clock signal at the network interface controller. Pursuant to the process, the bridge senses a timing of the delayed reference clock signal. The process includes communicating management traffic between a network interface of a baseboard management controller and the network interface controller via the interconnect. The communication of the management traffic includes the port, responsive to the sensing of the timing of the delayed reference clock signal, synchronizing communication of data with the first end of the interconnect to the delayed reference clock signal.