The present disclosure relates to a data driving device and a method of driving the data driving device and, more particularly, to a data driving device and a method of driving the same in which a tuning of a set value of an internal circuit is automatically performed.

A signal receiving device may include a high-speed receiving circuit, a low-speed receiving circuit, a low-speed synchronization circuit and a low-speed synchronization circuit. The high-speed receiving circuit receives an input signal and generate a high-speed received signal in a first operation mode. The high-speed synchronization circuit generates a high-speed synchronized signal to synchronize the high-speed received signal with a clock signal. The low-speed receiving circuit receives the input signal and generate a low-speed received signal in a second operation mode. The low-speed synchronization circuit generates a low-speed synchronized signal to synchronize the low-speed received signal with the clock signal. According to an operation mode, one of the high-speed synchronized signal and the low-speed synchronized signal is selected as an internal signal.

A signal receiving device may include a high-speed receiving circuit, a low-speed receiving circuit, a low-speed synchronization circuit and a low-speed synchronization circuit. The high-speed receiving circuit receives an input signal and generate a high-speed received signal in a first operation mode. The high-speed synchronization circuit generates a high-speed synchronized signal to synchronize the high-speed received signal with a clock signal. The low-speed receiving circuit receives the input signal and generate a low-speed received signal in a second operation mode. The low-speed synchronization circuit generates a low-speed synchronized signal to synchronize the low-speed received signal with the clock signal. According to an operation mode, one of the high-speed synchronized signal and the low-speed synchronized signal is selected as an internal signal.

A circuit interface includes one or more processors that generate opcodes, a plurality of interface control circuits, each including a respective processing element responsive to the opcodes generated by one or more processors. Each interface control circuit corresponds to a respective link of a plurality of links of a device-to-device interface (DDI), and each link of the plurality of links of the DDI is for transmitting or receiving signals from one or more sources or one or more destinations external to the circuit.

A circuit interface includes one or more processors that generate opcodes, a plurality of interface control circuits, each including a respective processing element responsive to the opcodes generated by one or more processors. Each interface control circuit corresponds to a respective link of a plurality of links of a device-to-device interface (DDI), and each link of the plurality of links of the DDI is for transmitting or receiving signals from one or more sources or one or more destinations external to the circuit.

The present disclosure provides a control device having versatility and extensibility of a load driving circuit. A control device includes a processor and an IC, in which the IC includes: a communication circuit that transmits a control signal from the processor; a first drive circuit that drives a first load; a second drive circuit that drives a second load and is provided outside the IC separately from the first drive circuit; and a third drive circuit that controls the second drive circuit, the processor transmits channel information corresponding to the number of switches of the second drive circuit to the IC, and the communication circuit changes the number of channels of the third drive circuit on the basis of the channel information.

An adjustable high resolution timer (100) for synchronizing a local clock to an external reference clock includes frequency offset acquisition and compensation unit (110) configured to acquire a frequency offset difference between the local and external reference clock and to generate frequency adjustment signals based on the frequency offset difference; a time drift tracking and adjustment unit (120) configured to continuously monitor the local and external reference clocks for phase offset differences therebetween and to generate timing adjustment signals based on the phase offset difference; a nanosecond timer core unit (140) configured to generate a frequency and phase adjusted nanosecond timer output signal in response to the frequency adjustment signals and timing adjustment signals; and a pulse generation unit (130) for generating a plurality of output pulse signals that are synchronized with the external reference clock in response to the frequency and phase adjusted nanosecond timer output signal.

An adjustable high resolution timer (100) for synchronizing a local clock to an external reference clock includes frequency offset acquisition and compensation unit (110) configured to acquire a frequency offset difference between the local and external reference clock and to generate frequency adjustment signals based on the frequency offset difference; a time drift tracking and adjustment unit (120) configured to continuously monitor the local and external reference clocks for phase offset differences therebetween and to generate timing adjustment signals based on the phase offset difference; a nanosecond timer core unit (140) configured to generate a frequency and phase adjusted nanosecond timer output signal in response to the frequency adjustment signals and timing adjustment signals; and a pulse generation unit (130) for generating a plurality of output pulse signals that are synchronized with the external reference clock in response to the frequency and phase adjusted nanosecond timer output signal.

A clock data recovery circuit includes a circuit that receives a data signal for which each of a plurality of potential levels is associated with a value of 2 bits or more, based on a result of a first comparison that compares the 3 or more first thresholds with the data signal at timing synchronized with a clock signal; a circuit that outputs a result of a second comparison that compares the data signal with a second threshold at the timing; a circuit that generates a phase difference signal indicating whether to advance or delay a phase of the clock signal, based on the result of the determination and the result of the second comparison; a filter that generates a phase adjusted value indicating an adjustment amount of the phase, based on the phase difference signal; and a circuit that adjusts the phase based on the phase adjusted value.

A clock data recovery circuit includes a circuit that receives a data signal for which each of a plurality of potential levels is associated with a value of 2 bits or more, based on a result of a first comparison that compares the 3 or more first thresholds with the data signal at timing synchronized with a clock signal; a circuit that outputs a result of a second comparison that compares the data signal with a second threshold at the timing; a circuit that generates a phase difference signal indicating whether to advance or delay a phase of the clock signal, based on the result of the determination and the result of the second comparison; a filter that generates a phase adjusted value indicating an adjustment amount of the phase, based on the phase difference signal; and a circuit that adjusts the phase based on the phase adjusted value.