Patent classifications
H04L7/02
SKEW DETECTION AND CORRECTION FOR ORTHOGONAL DIFFERENTIAL VECTOR SIGNALING CODES
Methods and systems are described for receiving a plurality of signals corresponding to symbols of a codeword on a plurality of wires of a multi-wire bus, and responsively generating a plurality of sub-channel outputs using a plurality of multi-input comparators (MICs) connected to the plurality of wires of the multi-wire bus, generating a plurality of wire-specific skew control signals, each wire-specific skew control signal of the plurality of wire-specific skew control signals generated by combining (i) one or more sub-channel specific skew measurement signals associated with corresponding sub-channel outputs undergoing a transition and (ii) a corresponding wire-specific transition delta, and providing the plurality of wire-specific skew control signals to respective wire-skew control elements to adjust wire-specific skew.
SKEW DETECTION AND CORRECTION FOR ORTHOGONAL DIFFERENTIAL VECTOR SIGNALING CODES
Methods and systems are described for receiving a plurality of signals corresponding to symbols of a codeword on a plurality of wires of a multi-wire bus, and responsively generating a plurality of sub-channel outputs using a plurality of multi-input comparators (MICs) connected to the plurality of wires of the multi-wire bus, generating a plurality of wire-specific skew control signals, each wire-specific skew control signal of the plurality of wire-specific skew control signals generated by combining (i) one or more sub-channel specific skew measurement signals associated with corresponding sub-channel outputs undergoing a transition and (ii) a corresponding wire-specific transition delta, and providing the plurality of wire-specific skew control signals to respective wire-skew control elements to adjust wire-specific skew.
Client device and local clock skew compensation method thereof
A local watch skew compensation device of the present invention is a client device which is synchronized with the other client device to provide a time-aware service including: a local time providing unit which supplies first local time data and second local time data in accordance with a local clock; a media scheduling unit which receives first media data and second media data from the other client device, schedules first playout time of the first media data using the first local time data, and schedules second playout time of the second media data using the second local time data; and a skew monitoring unit which requests global time data to a global time server when a difference between the first playout time and the second playout time exceeds a skew threshold value, and the first media data and the second media data are different types of media data.
Synchronization for subcarrier communication
Methods, systems, and apparatus, including computer programs encoded on computer storage media, for clock synchronizing an optical system and multiple leaf systems. In some implementations, an apparatus includes a receiver comprising: a local oscillator laser providing a local oscillator signal, a detector circuit operable to receive a first optical signal and detect first data carried by the first optical signal based on the local oscillator signal, a reference clock circuit supplying a clock signal, a digital signal processor (DSP) operable to receive the first data and supply a control signal to the reference clock circuit based on the first data, the reference clock circuit being operable to adjust the clock signal based on the control signal; and a transmitter operable to output a second optical signal carrying second data, the second data having an associated rate that is based on the clock signal.
Dynamic timing recovery bandwidth modulation for phase offset mitigation
An apparatus may include a sampling circuit configured to produce a sequence of input samples based on a continuous time input signal and a sample clock signal, the sampling phase of the sequence of input samples based on a phase control value output by a timing recovery circuit. In addition, the apparatus may include the timing recovery circuit configured to receive the sequence of input samples, detect, for a current sample of the sequence of input samples, a phase offset in the sampling phase of the sequence of input samples, the phase offset being a deviation of the sampling phase from an expected phase, and in response to detecting the phase offset, select a bandwidth for timing recovery. Further, the timing recovery circuit may generate an updated phase control value based on the selected bandwidth for timing recovery.
Active load modulation transceiver
In accordance with a first aspect of the present disclosure, an active load modulation (ALM) transceiver is provided, comprising a transmitter configured to send a transmit signal to an external device, wherein the transceiver is configured to adjust one or more parameters of the transmit signal at the end of at least one burst of said transmit signal. In accordance with a second aspect of the present disclosure, a method of operating an active load modulation (ALM) transceiver is conceived, comprising sending, by a transmitter of the transceiver, a transmit signal to an external device, and adjusting, by the transceiver, one or more parameters of the transmit signal at the end of at least one burst of said transmit signal.
Active load modulation transceiver
In accordance with a first aspect of the present disclosure, an active load modulation (ALM) transceiver is provided, comprising a transmitter configured to send a transmit signal to an external device, wherein the transceiver is configured to adjust one or more parameters of the transmit signal at the end of at least one burst of said transmit signal. In accordance with a second aspect of the present disclosure, a method of operating an active load modulation (ALM) transceiver is conceived, comprising sending, by a transmitter of the transceiver, a transmit signal to an external device, and adjusting, by the transceiver, one or more parameters of the transmit signal at the end of at least one burst of said transmit signal.
WIRED COMMUNICATION SYSTEM INCLUDING ASYMMETRICAL PHYSICAL LAYER DEVICES
A first physical layer device includes a first transmitter and a first receiver. The first transmitter transmits first data to a second physical layer device over a medium at a first line rate during a first transmit period. The first receiver is configured to not receive data during the first transmit period and an echo reflection period occurring after the first transmit period. The echo reflection period is based on a length of the medium between the first physical layer device and the second physical layer device. The first receiver is configured to, after the echo reflection period, receive second data from the second physical layer device over the medium at a second line rate that is less than the first line rate.
WIRED COMMUNICATION SYSTEM INCLUDING ASYMMETRICAL PHYSICAL LAYER DEVICES
A first physical layer device includes a first transmitter and a first receiver. The first transmitter transmits first data to a second physical layer device over a medium at a first line rate during a first transmit period. The first receiver is configured to not receive data during the first transmit period and an echo reflection period occurring after the first transmit period. The echo reflection period is based on a length of the medium between the first physical layer device and the second physical layer device. The first receiver is configured to, after the echo reflection period, receive second data from the second physical layer device over the medium at a second line rate that is less than the first line rate.
Methods and apparatus for data synchronization in systems having multiple clock and reset domains
A data synchronization unit including first flip-flops, operating on a first clock domain and a reset of a second clock domain, sampling data from the first clock domain; a second flip-flop, operating in the first clock domain, sampling a request signal when enabled by a request pulse; a request signal path configured to delay the request signal by a first delay and to generate an enable signal for recirculation multiplexers in accordance with the delayed request signal; a reset signal synchronization path configured to delay the reset signal of the first clock domain by a second delay, wherein the second delay is shorter than the first delay; and multiplexers having first inputs for receiving outputs of the recirculation multiplexers, a second input for receiving a reset value of a programmable register, the multiplexers being configured to selectively output signals at inputs to outputs.