Systems, devices, and methods related to selecting a sample phase of a signal are disclosed. A method includes sampling a signal including a plurality of symbols with a plurality of different sample phases to obtain sample values of each of the plurality of symbols at each of the plurality of different sample phases. The signal is received from a shared transmission medium. The method also includes determining an edge sample phase of the plurality of different sample phases that corresponds to edges of the symbols based on the sample values. The method further includes determining a center sample phase of the plurality of different sample phases based on the determined edge sample phase, and using the determined center sample phase to determine values of the symbols.

Systems, devices, and methods related to selecting a sample phase of a signal are disclosed. A method includes sampling a signal including a plurality of symbols with a plurality of different sample phases to obtain sample values of each of the plurality of symbols at each of the plurality of different sample phases. The signal is received from a shared transmission medium. The method also includes determining an edge sample phase of the plurality of different sample phases that corresponds to edges of the symbols based on the sample values. The method further includes determining a center sample phase of the plurality of different sample phases based on the determined edge sample phase, and using the determined center sample phase to determine values of the symbols.

Disclosed are systems and devices for interfacing media access tuning circuitry that implements collision handling or traffic shaping with a reduced media independent interface (RMII). In some embodiments, an interface circuitry manages emulated signals generated by a media access tuning circuitry in response to detecting that the emulated signals would cause incorrect operation of an RMII. Also disclosed is a physical layer (PHY) device for a multidrop network. In some embodiments the PHY device implements physical layer collision techniques and operable to communicate with a media access control (MAC) device via an RMII, where the MAC is configured for carrier-sense multiple access (CSMA), CSMA with collision detection (CSMA/CD), or CSMA with collision avoidance (CSMA/CA). Also disclosed are processes for managing signaling at a PHY that implements physical layer collision avoidance (PLCA) or traffic shaping, as the case may be.

Disclosed are systems and devices for interfacing media access tuning circuitry that implements collision handling or traffic shaping with a reduced media independent interface (RMII). In some embodiments, an interface circuitry manages emulated signals generated by a media access tuning circuitry in response to detecting that the emulated signals would cause incorrect operation of an RMII. Also disclosed is a physical layer (PHY) device for a multidrop network. In some embodiments the PHY device implements physical layer collision techniques and operable to communicate with a media access control (MAC) device via an RMII, where the MAC is configured for carrier-sense multiple access (CSMA), CSMA with collision detection (CSMA/CD), or CSMA with collision avoidance (CSMA/CA). Also disclosed are processes for managing signaling at a PHY that implements physical layer collision avoidance (PLCA) or traffic shaping, as the case may be.

Methods, systems, transceivers, and apparatus are included for clock synchronizing an optical system and multiple leaf systems. In some implementations, a transceiver includes a receiver and a transmitter. The receiver includes an optical hybrid circuit operable to receive a first modulated optical signal and local oscillator light and to supply optical mixing products based on the first modulated optical signal and the local oscillator light. A photodiode circuit operable to supply an electrical signal based on the optical mixing products. An analog-to-digital conversion circuitry operable to supply digital signals based on the electrical signal. A digital signal processor operable to generate a supply signal based on the digital signals and provide the supply signal to a reference clock circuit for generating a clock signal. The transmitter is operable to output a second modulated optical signal that includes a timing of data based on the clock signal.

The present disclosure relates to a testing device and techniques of testing semiconductor structures and, more particularly, to an absolute phase measurement testing device and technique of testing semiconductor structures. The structure includes: a first frequency input source which provides a first signal to an up-converter at an input side of a test fixture; a down-converter on an output side of the test fixture; a second frequency signal source which provides a second signal at a higher frequency than the first signal to the up-converter and the down-converter on the output side of the test fixture; a bypass path which bypasses the test fixture and provides connection between the up-converter and the down-converter; and a digitizer that is connected to an output side of the down-converter.

The present disclosure relates to a testing device and techniques of testing semiconductor structures and, more particularly, to an absolute phase measurement testing device and technique of testing semiconductor structures. The structure includes: a first frequency input source which provides a first signal to an up-converter at an input side of a test fixture; a down-converter on an output side of the test fixture; a second frequency signal source which provides a second signal at a higher frequency than the first signal to the up-converter and the down-converter on the output side of the test fixture; a bypass path which bypasses the test fixture and provides connection between the up-converter and the down-converter; and a digitizer that is connected to an output side of the down-converter.

A synchronizer circuit includes a first synchronizer having a first input for receiving a signal associated with a first clock signal, a second input for receiving a second clock signal, and an output for providing a synchronizer circuit output signal; a second synchronizer having a first input for receiving the signal associated with the first clock signal, a second input for receiving the second clock signal, and an output; a detection stage having a first input coupled to the output of the first synchronizer and to the output of the second synchronizer, a second input for receiving the second clock signal, and an output; and a fault output stage having a first input coupled to the detection stage, a second input for receiving the second clock signal, and an output for providing a fault output signal.

A clock data recovery circuit includes a circuit that receives a data signal for which each of a plurality of potential levels is associated with a value of 2 bits or more, based on a result of a first comparison that compares the 3 or more first thresholds with the data signal at timing synchronized with a clock signal; a circuit that outputs a result of a second comparison that compares the data signal with a second threshold at the timing; a circuit that generates a phase difference signal indicating whether to advance or delay a phase of the clock signal, based on the result of the determination and the result of the second comparison; a filter that generates a phase adjusted value indicating an adjustment amount of the phase, based on the phase difference signal; and a circuit that adjusts the phase based on the phase adjusted value.

A clock data recovery circuit includes a circuit that receives a data signal for which each of a plurality of potential levels is associated with a value of 2 bits or more, based on a result of a first comparison that compares the 3 or more first thresholds with the data signal at timing synchronized with a clock signal; a circuit that outputs a result of a second comparison that compares the data signal with a second threshold at the timing; a circuit that generates a phase difference signal indicating whether to advance or delay a phase of the clock signal, based on the result of the determination and the result of the second comparison; a filter that generates a phase adjusted value indicating an adjustment amount of the phase, based on the phase difference signal; and a circuit that adjusts the phase based on the phase adjusted value.