Some embodiments include apparatuses and methods using a clock generator to generate clock signals, the clock signals being out of phase with each other; a transmitting circuit to provide patterns of data at an output of the transmitting circuit responsive to timing of the clock signals; and calculation and control circuitry to calculate an integral nonlinearity vector that represents offsets of transitions of the patterns from respective target positions, and to generate control information based on the integral nonlinearity vector to adjust phases of the clock signals based on the control information.

MicroLEDs may be used for short-range optical communications. Signal equalization may be used to decrease distortion in transmitted and/or received information, including with the use of multi-level modulation formats.

MicroLEDs may be used for short-range optical communications. Signal equalization may be used to decrease distortion in transmitted and/or received information, including with the use of multi-level modulation formats.

A clock-and-data recovery circuit for serial receiver includes a jitter meter and an adaptive loop gain adjustment circuitry. The clock-recovery circuitry phase aligns a clock signal to the incoming data. A jitter meter provides a measure of jitter, while adaption circuitry uses the measure to adjust the clock-recovery circuity in a manner that reduces clock jitter. The jitter measure can be a ratio of errors associated with different inter-symbol slew rates.

A clock-and-data recovery circuit for serial receiver includes a jitter meter and an adaptive loop gain adjustment circuitry. The clock-recovery circuitry phase aligns a clock signal to the incoming data. A jitter meter provides a measure of jitter, while adaption circuitry uses the measure to adjust the clock-recovery circuity in a manner that reduces clock jitter. The jitter measure can be a ratio of errors associated with different inter-symbol slew rates.

Magnetic sensor synchronization techniques for pose tracking in artificial reality systems include managing and sending, by one or more primary magnetic sensors, a wireless synchronization signal to other magnetic sensors to trigger sensing sampling. The primary magnetic sensor may generate and send sensor data to a wireless data hub that operates as a sensor data collector and transmits data for pose tracking in the system. Each of the other (non-primary) magnetic sensors, in response to receiving the wireless synchronization signal, updates its sampling starting clock based on new synchronization timing. Each of the magnetic sensors sends generated sensor data to its corresponding primary sensor or wireless data hub according to a different schedule to avoid conflicts between the various magnetic sensors. The synchronization process may be repeated a number of times if a sensor fails to receive or respond to a synchronization signal.

Magnetic sensor synchronization techniques for pose tracking in artificial reality systems include managing and sending, by one or more primary magnetic sensors, a wireless synchronization signal to other magnetic sensors to trigger sensing sampling. The primary magnetic sensor may generate and send sensor data to a wireless data hub that operates as a sensor data collector and transmits data for pose tracking in the system. Each of the other (non-primary) magnetic sensors, in response to receiving the wireless synchronization signal, updates its sampling starting clock based on new synchronization timing. Each of the magnetic sensors sends generated sensor data to its corresponding primary sensor or wireless data hub according to a different schedule to avoid conflicts between the various magnetic sensors. The synchronization process may be repeated a number of times if a sensor fails to receive or respond to a synchronization signal.

The present disclosure discloses a clock and data recovery circuit. The clock and data recovery circuit may include a clock recovery unit configured to output a recovery clock signal by operating a first time-to-digital conversion circuit or a second time-to-digital conversion circuit depending on a phase difference between a clock of an input signal and the recovery clock signal, and a data recovery unit configured to sample data from the input signal and output recovery data.

The present disclosure discloses a clock and data recovery circuit. The clock and data recovery circuit may include a clock recovery unit configured to output a recovery clock signal by operating a first time-to-digital conversion circuit or a second time-to-digital conversion circuit depending on a phase difference between a clock of an input signal and the recovery clock signal, and a data recovery unit configured to sample data from the input signal and output recovery data.

Solution for reducing timing uncertainty is provided. The solution means for receiving data in a first clock domain; means for selecting in the first clock domain a data unit to be a frame starting point and transmitting the information on the selection to a frame counter in a second clock domain; means for performing to the data in a coding/decoding unit coding or decoding, the coding/decoding unit several clock domains; means for obtaining at the output of the coding/decoding unit the position of the selected frame starting point; and means for determining timing of the correct frame starting point of the coded/decoded data utilising the obtained position of the selected frame starting point and the information in the frame counter.