Methods, systems, and storage media for synchronizing network devices are disclosed herein. An embodiment may include sending a control signal to each of multiple devices that have device operations that are perceptible together, the control signal to control the perceptible device operation of each device. Timing information may be received from each device indicating timing of perceptible operation of the device relative to the control signal. Synchronizing control signals may be determined from the timing information to control the device operations to be perceptibly synchronous, and the synchronizing control signals may be sent to the devices to provide perceptibly synchronous operation of them.

Methods, systems, and storage media for synchronizing network devices are disclosed herein. An embodiment may include sending a control signal to each of multiple devices that have device operations that are perceptible together, the control signal to control the perceptible device operation of each device. Timing information may be received from each device indicating timing of perceptible operation of the device relative to the control signal. Synchronizing control signals may be determined from the timing information to control the device operations to be perceptibly synchronous, and the synchronizing control signals may be sent to the devices to provide perceptibly synchronous operation of them.

A method of detecting transient changes in the distribution of a discrete time series includes: operating in a sparse mode wherein, at sniff periods successively repeated at a first rate, at most K test phases are performed, K being an integer superior or equal to two, each test phase consisting of analyzing, by a sampling stopping time determination unit, samples of the time series captured by a sampler at sampling times according to a second rate which is higher than the first rate to provide a positive or negative result of the test phase. If the results of K successive test phases of a sniff period are each positive, the method switches to operate in a dense mode wherein the sampler is operated to continuously capture samples of the time series at sampling times according to the second sampling rate.

A digital communication interface includes a deserializer module, a gearbox module, and a parallel communication channel connecting the gearbox module to the deserializer module. The deserializer module has a fixed deserialization factor. The gearbox module has a temporal translation factor to change bit-length of words received through the parallel communication channel to bit-length suitable for a downstream data path.

In one embodiment, a method comprises receiving, by a network device, one or more advertisement messages comprising timing information describing a quality of a network clock that is originated by a master clock device at a root of a directed acyclic graph (DAG); the network device executing an objective function for the DAG providing an optimized loopless time topology for the network clock, synchronized to the master clock device, based on the timing information; and the network device attaching to a parent device in the DAG based on the objective function, for optimized generation of the network clock by the network device.

A method of calibrating a high frequency signal measurement system is described. The measurement system is in the form of a network analyzer (6) and has first and second phase-locked signal sources (SS1 & SS2) and at least two measurement receivers (18a, 18b). A phase meter (26) is provided. A reference signal (F0) is outputted at a first frequency from the first signal source (SS1). The second signal source (SS2) steps through a multiplicity of different test frequencies (nF0), being phase-locked with the reference signal (F0), which are applied in turn to a part of the measurement system. Measurements are taken, via the two measurement receivers (18a, 18b), of characteristics of the resulting signal at a measurement plane. The absolute phase of the signal at the measurement plane is also measured with the phase meter (26). Calibration data is generated which relates the characteristics of the signals as measured by the measurement system (6) and the absolute phase as measured with the phase meter (26).

An Ethernet Physical Layer (PHY) device includes a link interface and a transceiver. The link interface connects to a full-duplex wired Ethernet link. The transceiver receives first Ethernet signals carrying first data at a first data rate over toe Ethernet link at a first baud rate, transmits second Ethernet signals carrying second data at a second data rate higher than the first data rate, over the Ethernet link, at a second baud rate that is higher than the first baud rate, resamples a reference signal related to the second Ethernet signals to match the first baud rate, generates from the resampled reference signal, at the first baud rate, an echo cancelation signal indicative of an echo signal originating from the second Ethernet signals and interfering with reception of the first Ethernet signals, and suppresses the echo signal from the first Ethernet signals using the echo cancelation signal.

An Ethernet Physical Layer (PHY) device includes a link interface and a transceiver. The link interface connects to a full-duplex wired Ethernet link. The transceiver receives first Ethernet signals carrying first data at a first data rate over toe Ethernet link at a first baud rate, transmits second Ethernet signals carrying second data at a second data rate higher than the first data rate, over the Ethernet link, at a second baud rate that is higher than the first baud rate, resamples a reference signal related to the second Ethernet signals to match the first baud rate, generates from the resampled reference signal, at the first baud rate, an echo cancelation signal indicative of an echo signal originating from the second Ethernet signals and interfering with reception of the first Ethernet signals, and suppresses the echo signal from the first Ethernet signals using the echo cancelation signal.

A communication device includes a sampler configured to sample an input signal, wherein the sampler is configured to generate a sampled value for each sampling time of a sequence of sampling times, a sequence value generator configured to generate an output value for each sampling time of the sequence of sampling times based on the sampled values, wherein the sequence value generator is configured to set the output value for a sampling time based on the sampled value for the sampling time and based on a limitation of the difference between the output value for the sampling time and the output value for the preceding sampling time in the sequence of sampling times, and an edge detector configured to detect an edge in the input signal based on the output values.

Various embodiments of methods and systems for data generator driven bus clock voting are disclosed. An exemplary embodiment defines a first timing domain within a system on a chip to comprise a data generating component and a bus that includes a memory management unit. The bus serves to communicatively couple the data generating component to a memory component, such as a DDR. A second timing domain within the system on a chip comprises the memory component. With such a configuration, the embodiment may leverage the clock speed of the data generating component to set a clock speed for components in the first timing domain and, in doing so, the clock speed of the memory management unit is dictated by the first timing domain.