A transceiver includes a transmitter and a receiver connected to each other through a first line and a second line. The transmitter transmits signals having a first voltage range to the first line and the second line in a first mode, and transmits signals having a second voltage range less than the first voltage range to the first line and the second line in a second mode. In transmitting a (1-1)-th payload to the receiver, the transmitter is sequentially driven in the first mode, the second mode, and the first mode, and transmits a first clock training pattern and the (1-1)-th payload in the second mode. The receiver includes a clock data recovery circuit generating a first clock signal corresponding to the received first clock training pattern and a register storing first frequency information and first phase information of the first clock training pattern.

A method for synchronizing a data frame and data symbols in a communication system includes generating a training sequence including a serial sequence of data symbols that are conjugate symmetric, inserting the training sequence in a transmitter-side data frame, converting constituent data symbols of the transmitter-side data frame to communication signals, transmitting the communication signals from a transmitter to a receiver, converting the communication signals to a stream of received data symbols, detecting presence of the training sequence in the stream of received data symbols, and identifying a position of a received data frame from the presence of the training sequence.

A method of operating a data processing system to generate a jitter-injected signal from an input signal that is a function of time is disclosed. A time offset corresponding to a first time is generated according to a jitter specification that specifies the offset as a function of time. The jitter-injected signal at the first time is generated by evaluating the input signal at a time equal to a sum of the time offset and the first time. If the jitter specification only provides offsets at signal crossing times, interpolation is used to derive time offsets at non-signal crossing times.

In a reference signal generator including a synchronization circuit configured to convert a digital signal into an analog signal, supply this signal to a voltage controlled oscillator, and control the voltage controlled oscillator to obtain a signal synchronized with the reference signal, without an accumulation of quantization error in a holdover control in which an acquisition of a reference signal is not available. The reference signal generator includes a phase synchronization circuit and a controller. The phase synchronization circuit controls the reference signal outputted from the oscillator, according to a control signal obtained based on the reference signal. The controller generates a free-running control signal and controls the oscillator when the reference signal becomes unavailable. The oscillator receives discrete values and oscillates accordingly. A digital delta-sigma modulator configured to modulate the free-running control signal of the controller disposed in a subsequent stage of the controller.

In a reference signal generator including a synchronization circuit configured to convert a digital signal into an analog signal, supply this signal to a voltage controlled oscillator, and control the voltage controlled oscillator to obtain a signal synchronized with the reference signal, without an accumulation of quantization error in a holdover control in which an acquisition of a reference signal is not available. The reference signal generator includes a phase synchronization circuit and a controller. The phase synchronization circuit controls the reference signal outputted from the oscillator, according to a control signal obtained based on the reference signal. The controller generates a free-running control signal and controls the oscillator when the reference signal becomes unavailable. The oscillator receives discrete values and oscillates accordingly. A digital delta-sigma modulator configured to modulate the free-running control signal of the controller disposed in a subsequent stage of the controller.

A node synchronization method, includes: receiving a synchronization message by a first synchronization node in a network; determining whether to update a first local time of the first synchronization node according to the synchronization message by the first synchronization node; updating the first local time according to a synchronization time of the synchronization message by the first synchronization node when determining to update the first local time; and updating the synchronization time of the received synchronization message with the current first local time and forwarding the updated synchronization message by the first synchronization node.

Disclosed is receiver apparatus including a first input configured to receive a first signal, a second input configured to receive a second signal, a switching circuit configured to alternate between the first and second signal from the first and second inputs, a receiver configured to sample the input signal to produce a plurality of input samples, a reference sequence generator configured to generate a reference signal, and a correlator configured to correlate the first and second signals with the reference signal to detect a correlation event, the correlator including a first buffer configured to receive signals from the first input and a second buffer configured to receive signals from the second input, wherein the correlator is configured to process the first signal in the first buffer, while the second buffer receives the second signal.

System and method of timing recovery for recovering a clock signal by using adaptive channel response estimation. The channel response estimation in the timing recovery loop is dynamically adapted to the current channel response that varies over time. More particularly, the channel estimation coefficients used in a channel estimator can be adapted based on an error signal representing the difference between a received signal at the timing recovery loop and an estimated signal output from a channel estimator. Further, to prevent undesirable interaction between the channel estimator and the overall timing recovery loop with respect to clock phase recovery, the adaptation of channel estimation can be controlled in terms of speed or time so as to reduce or eliminate the channel estimator's effect on clock phase correction.

System and method of timing recovery for recovering a clock signal by using adaptive channel response estimation. The channel response estimation in the timing recovery loop is dynamically adapted to the current channel response that varies over time. More particularly, the channel estimation coefficients used in a channel estimator can be adapted based on an error signal representing the difference between a received signal at the timing recovery loop and an estimated signal output from a channel estimator. Further, to prevent undesirable interaction between the channel estimator and the overall timing recovery loop with respect to clock phase recovery, the adaptation of channel estimation can be controlled in terms of speed or time so as to reduce or eliminate the channel estimator's effect on clock phase correction.

A packaged circuit including a digital controller, a port physical layer and a digital coding circuit is provided. The digital controller outputs digital data in parallel via a parallel data channel, and the digital data includes a plurality of data bits. The port physical layer includes a clock generator, and outputs a data signal according to the data bits. The clock generator outputs a clock signal to the digital controller. The digital coding circuit is coupled to the digital controller and the port physical layer, and receives the digital data and the clock signal. The digital coding circuit codes the clock signal to generate a plurality of clock bits, and outputs the clock bits to the port physical layer. The port physical layer converts the clock bits into an output clock and outputs the output clock.