A handshaking process for time-reversal wireless communication is provided. A first device receives a handshake signal transmitted from a second device through multiple propagation paths, the handshake signal including a preamble and a training sequence, in which the training sequence includes a sequence of symbols known to the first and second devices. A synchronization index is determined based on the preamble, and the training sequence in the handshake signal is identified based on the synchronization index. A channel response signal is determined based on the received training sequence, and a signature waveform that is a time-reversed signal of the channel response signal is generated. A transmission signal is generated based on transmit data and the signature waveform, in which the transmit data are data configured to be transmitted to the second device.

A method generates an asynchronous trigger signal in a position-measuring device having a position-sensing unit, a processing unit and an interface unit. The position-measuring device is connectable via the interface unit and a bidirectional data channel to subsequent electronics for communication purposes. A synchronous data stream is generated from an asynchronous data stream arriving at the position-measuring device from a direction of the subsequent electronics by sampling the asynchronous data stream in a time pattern of a clock signal. A gate signal is generated upon an enable condition for outputting the trigger signal being detected by evaluating the synchronous data stream. The asynchronous trigger signal is generated upon the gate signal being present and a signal edge of the asynchronous data stream occurring.

A line card of a network box receives a SYNC input signal and generates a first time stamp based on receipt of the SYNC input signal. The line card generates a system clock signal in a phase-locked loop and generates a SYNC output signal by dividing the system clock signal in a divider circuit. The SYNC output signal is fed back to an input terminal as a SYNC feedback signal. A time stamp is generated based on receipt of the SYNC feedback signal. The line card determines a time between the SYNC input signal and the SYNC feedback signal based on the first time stamp and the second time stamp. The timing of the SYNC output signal is adjusted based on the time difference using a coarse time adjustment by adjusting a divide ratio of the divider circuit and using a fine time adjustment in the phase-locked loop based on a residue of a remainder of the time difference not accounted for by the coarse time adjustment.

A line card of a network box receives a SYNC input signal and generates a first time stamp based on receipt of the SYNC input signal. The line card generates a system clock signal in a phase-locked loop and generates a SYNC output signal by dividing the system clock signal in a divider circuit. The SYNC output signal is fed back to an input terminal as a SYNC feedback signal. A time stamp is generated based on receipt of the SYNC feedback signal. The line card determines a time between the SYNC input signal and the SYNC feedback signal based on the first time stamp and the second time stamp. The timing of the SYNC output signal is adjusted based on the time difference using a coarse time adjustment by adjusting a divide ratio of the divider circuit and using a fine time adjustment in the phase-locked loop based on a residue of a remainder of the time difference not accounted for by the coarse time adjustment.

Advanced detectors for vector signaling codes are disclosed which utilize multi-input comparators, generalized on-level slicing, reference generation based on maximum swing, and reference generation based on recent values. Vector signaling codes communicate information as groups of symbols which, when transmitted over multiple communications channels, may be received as mixed sets of symbols from different transmission groups due to propagation time variations between channels. Systems and methods are disclosed which compensate receivers and transmitters for these effects and/or utilize codes having increased immunity to such variations, and circuits are described that efficiently implement their component functions.

A method may comprise receiving and sampling a signal. The signal may encode a data packet. A slice may be generated and stored comprising a pair of values for each of a selected number of samples of the signal representing a correlation of the signal to reference functions in the receiver. The presence of the data packet may then be detected and the detected packet decoded from the stored slices. The generating and storing slices may be carried out as the received signal is sampled. The sampled values of the signal may be discarded as the slices are generated and stored. The slice representation of the signal can be manipulated to generate filters with flexible bandwidth and center frequency.

An LVDS data recovery method includes adopting three clocks to sample a received signal clock at the same time, wherein the first clock, the second clock and the third clock have the same frequency and different phases; determining whether the first clock is in the rising-falling edges of the received signal clock, in accordance with sampled levels of the received signal clock sampled by the three clocks at the same time; after determining the first clock is in the rising-falling edges of the received signal clock, adjusting phase of the first clock, and sampling the received data signal in accordance with adjusted phase of the first clock. The LVDS data recovery method ensures that the sampling clock edge is aligned with at the center of the data to be sampled. In case of high speed, the accuracy of the data sampling is guaranteed.

An LVDS data recovery method includes adopting three clocks to sample a received signal clock at the same time, wherein the first clock, the second clock and the third clock have the same frequency and different phases; determining whether the first clock is in the rising-falling edges of the received signal clock, in accordance with sampled levels of the received signal clock sampled by the three clocks at the same time; after determining the first clock is in the rising-falling edges of the received signal clock, adjusting phase of the first clock, and sampling the received data signal in accordance with adjusted phase of the first clock. The LVDS data recovery method ensures that the sampling clock edge is aligned with at the center of the data to be sampled. In case of high speed, the accuracy of the data sampling is guaranteed.

Embodiments of a data encryption and/or decryption technique are disclosed. Briefly, for example, in accordance with one example embodiment a method is provided. A message based at least in part on a hierarchical symbol assignment system is encrypted. The hierarchical symbol assignment system is represented as a numerical value.

Embodiments of a data encryption and/or decryption technique are disclosed. Briefly, for example, in accordance with one example embodiment a method is provided. A message based at least in part on a hierarchical symbol assignment system is encrypted. The hierarchical symbol assignment system is represented as a numerical value.