Apparatus and methods for multiphase clock generation are provided herein. In certain embodiments, a multiphase clock generator includes a first clock buffer that generates a first output clock signal based on a first input clock signal, a second clock buffer that generates a second output clock signal based on a second input clock signal, and a first clock interpolation circuit that generates a third output clock signal based on interpolating the first input clock signal and the second input clock signal. The first clock interpolation circuit generates the third output clock signal based on multiplying the first input clock signal by a first adjustable current to generate a first multiplied current, multiplying the second input clock signal by a second adjustable current to generate a second multiplied current, combining the first multiplied current and the second multiplied current to generate a combined current, and integrating the combined current.

Apparatus and methods for multiphase clock generation are provided herein. In certain embodiments, a multiphase clock generator includes a first clock buffer that generates a first output clock signal based on a first input clock signal, a second clock buffer that generates a second output clock signal based on a second input clock signal, and a first clock interpolation circuit that generates a third output clock signal based on interpolating the first input clock signal and the second input clock signal. The first clock interpolation circuit generates the third output clock signal based on multiplying the first input clock signal by a first adjustable current to generate a first multiplied current, multiplying the second input clock signal by a second adjustable current to generate a second multiplied current, combining the first multiplied current and the second multiplied current to generate a combined current, and integrating the combined current.

A transceiver includes a transmitter which transmits clock-embedded data through a line, where the clock-embedded data includes a clock training pattern, a start pattern, an encoded payload, and an end pattern, and a receiver which receives the clock-embedded data through the line, detects a clock embedding-related error from the clock-embedded data, and outputs an error flag corresponding to the clock embedding-related error to the transmitter.

A time synchronization system includes a master station (100) and slave stations (200) communicably connected to the master station (100). The master station (100) includes a contention determiner (114) and a time synchronization frame processing unit (113). The contention determiner (114) determines, based on receipt timings of a plurality of first time synchronization frames transmitted from the respective slave stations (200), whether the plurality of first time synchronization frames have a possibility of contention over relay processing. The time synchronization frame processing unit (113) discards, when the contention determiner (114) determines that the plurality of first time synchronization frames have the possibility of the contention, out of first time synchronization frames that have a possibility of mutual contention, a first time synchronization frame received later.

A time synchronization system includes a master station (100) and slave stations (200) communicably connected to the master station (100). The master station (100) includes a contention determiner (114) and a time synchronization frame processing unit (113). The contention determiner (114) determines, based on receipt timings of a plurality of first time synchronization frames transmitted from the respective slave stations (200), whether the plurality of first time synchronization frames have a possibility of contention over relay processing. The time synchronization frame processing unit (113) discards, when the contention determiner (114) determines that the plurality of first time synchronization frames have the possibility of the contention, out of first time synchronization frames that have a possibility of mutual contention, a first time synchronization frame received later.

Techniques, methods and system, for synchronization of sparse data signals are disclosed, comprising mixing a serial stream of sparse data signals with a serial stream of synchronization signals, to thereby add redundancy to the serial stream of sparse data signals and enable clock regeneration from a serial stream of mixed signals produced by said mixing, emulating the serial stream of synchronization signals by applying the clock regeneration to the serial stream of mixed signals, and generating a stream of parallel synchronization signals having a frequency of the serial stream of synchronization signals, deserializing the serial stream of mixed signals into a stream of parallel mixed signals having a data rate lower than a data rate of the serial signal streams, and demixing the stream of parallel synchronization signals with the stream of parallel mixed signals and thereby removing the redundancy introduced by the mixing into the sparse data signals and generating a parallel stream of demixed signals substantially synchronized with said synchronization signals.

Transmitters and methods of transmitting a polar-modulated signal include a driver to output a polar-modulated signal according to a phase-modulation signal and an amplitude-modulation signal. A voltage regulator is connected to the driver, with the amplitude-modulation signal controlling an input of the voltage regulator and with the amplitude-modulation signal further being combined with an output of the voltage regulator to control an amplitude of the output of the driver to compensate for bandwidth cutoff noise in the voltage regulator.

Transmitters and methods of transmitting a polar-modulated signal include a driver to output a polar-modulated signal according to a phase-modulation signal and an amplitude-modulation signal. A voltage regulator is connected to the driver, with the amplitude-modulation signal controlling an input of the voltage regulator and with the amplitude-modulation signal further being combined with an output of the voltage regulator to control an amplitude of the output of the driver to compensate for bandwidth cutoff noise in the voltage regulator.

In one embodiment, a method receives a first time from a network device. The first time is derived from a first timing source in a first domain. The method receives a second time in a second domain from a second timing source. A difference time value is calculated between the first time and the second time. The method then sends the difference time value to the network device where the network device uses the difference time value to send a delay value to other computing devices to synchronize timing of the other computing devices in the second domain. The other computing devices are configured to synchronize the respective time using the delay value with mobile network devices to allow timing synchronization between the mobile network devices.

Systems and methods are presented that offer significant improvements in the performance of time division duplex (TDD) systems by utilizing an adaptive synchronous protocol. Conventional TDD systems are limited because data is transmitted during discreet and limited intervals of time, and because TDD transceivers may not simultaneously transmit and receive for reasons of insufficiently separated frequencies and limited receiver selectivity. Typically, TDD systems have significant latency due to the time to change from transmission to reception and the propagation delay time. By synchronizing the master nodes and the one or more remotes and by scheduling the traffic loads between these nodes, remote nodes may begin transmitting before the master node is finished with its transmission, and vice versa. This method reduces latency and improves the frame efficiency. Further, the frame efficiency may improve as the distance from the master node to the remote node increases.