A communication apparatus is provided and receives a communication packet, acquires a timestamp of a reception of the communication packet, analyzes a type of the received communication packet, transfers the received communication packet to a predetermined memory based on information indicating an analyzed type of the communication packet, and associates the analyzed type of the communication packet with the acquired timestamp.

A physiological information system includes: a plurality of physiological information sensors configured to acquire physiological information data of a subject being tested, and a physiological information processing apparatus communicatively connected to each of the plurality of physiological information sensors. The physiological information processing apparatus is configured to transmit a synchronous packet toward each of the plurality of physiological information sensors. Each of the plurality of physiological information sensors is configured to: acquire the physiological information data of the subject being tested; receive the synchronous packet transmitted from the physiological information processing apparatus or a trigger signal associated with the synchronous packet; start AD conversion processing for the acquired physiological information data when receiving the synchronous packet or the trigger signal; and transmit the physiological information data converted into digital data to the physiological information processing apparatus.

A physiological information system includes: a plurality of physiological information sensors configured to acquire physiological information data of a subject being tested, and a physiological information processing apparatus communicatively connected to each of the plurality of physiological information sensors. The physiological information processing apparatus is configured to transmit a synchronous packet toward each of the plurality of physiological information sensors. Each of the plurality of physiological information sensors is configured to: acquire the physiological information data of the subject being tested; receive the synchronous packet transmitted from the physiological information processing apparatus or a trigger signal associated with the synchronous packet; start AD conversion processing for the acquired physiological information data when receiving the synchronous packet or the trigger signal; and transmit the physiological information data converted into digital data to the physiological information processing apparatus.

A clock data recovery circuit includes the following elements: a phase detector for outputting a phase adjustment signal by comparing a clock signal of a first node and an input signal; a charge pump for adjusting a charge amount of a second node according to the phase adjustment signal; a first switch including one end coupled to the second node and including another end coupled to a third node; a second switch including one end which receives a bias voltage and including another end coupled to the third node; a capacitor including a first electrode coupled to the third node; third switches; and voltage control oscillators including control terminals coupled to the third node and including output terminals coupled to the first node through the third switches.

An input signal arranged in frames is received. The frames include a cyclic redundancy check (CRC) field including a number of bits having bit edges. A timing signal is generated to include adjustable duration waveforms at one of a first duration value and a second duration value. A CRC check determines the occurrence, over the duration, of a number of waveforms of the timing signal having their duration adjusted to one of the first duration value and the second duration value which corresponds to the number of bits. A check signal is produced having a pass/fail value. If pass, the duration of the waveforms in the timing signal is maintained adjusted to the one of the first duration value and the second duration value. If fail, the duration of the waveforms in the timing signal is re-adjusted to the other of the first duration value and the second duration value.

A time synchronization system includes a master station (100) and slave stations (200) communicably connected to the master station (100). The master station (100) includes a contention determiner (114) and a time synchronization frame processing unit (113). The contention determiner (114) determines, based on receipt timings of a plurality of first time synchronization frames transmitted from the respective slave stations (200), whether the plurality of first time synchronization frames have a possibility of contention over relay processing. The time synchronization frame processing unit (113) discards, when the contention determiner (114) determines that the plurality of first time synchronization frames have the possibility of the contention, out of first time synchronization frames that have a possibility of mutual contention, a first time synchronization frame received later.

A time synchronization system includes a master station (100) and slave stations (200) communicably connected to the master station (100). The master station (100) includes a contention determiner (114) and a time synchronization frame processing unit (113). The contention determiner (114) determines, based on receipt timings of a plurality of first time synchronization frames transmitted from the respective slave stations (200), whether the plurality of first time synchronization frames have a possibility of contention over relay processing. The time synchronization frame processing unit (113) discards, when the contention determiner (114) determines that the plurality of first time synchronization frames have the possibility of the contention, out of first time synchronization frames that have a possibility of mutual contention, a first time synchronization frame received later.

A forward error correction (FEC) decoder is configured to find an alignment of a code block in a data stream by attempting to fully or partially decode one or more data windows of a predetermined size in the data stream. The predetermined size is a size of each codeword. The FEC decoder selects a first data window of the predetermined size, attempts to decode the first data window based on a particular error control coding method, and determines whether a valid codeword can be identified by attempting to decode the first data window. In response to determining that a valid codeword can be identified, the FEC decoder determines that an alignment of the codeword with the first data window is found. Otherwise, the FEC decoder selects a second data window of the predetermined size and attempts to decode the second data window.

A method and system that provides for execution of a first calibration sequence, such as upon initialization of a system, to establish an operation value, which utilizes an algorithm intended to be exhaustive, and executing a second calibration sequence from time to time, to measure drift in the parameter, and to update the operation value in response to the measured drift. The second calibration sequence utilizes less resources of the communication channel than does the first calibration sequence. In one embodiment, the first calibration sequence for measurement and convergence on the operation value utilizes long calibration patterns, such as codes that are greater than 30 bytes, or pseudorandom bit sequences having lengths of 2.sup.N−1 bits, where N is equal to or greater than 7, while the second calibration sequence utilizes short calibration patterns, such as fixed codes less than 16 bytes, and for example as short as 2 bytes long.

A line card receives a SYNC input signal and a first system clock signal. The line card generates a second system clock signal in a PLL and generates a SYNC output signal by dividing the second system clock signal in a divider circuit. The SYNC output signal is fed back as a SYNC feedback signal. The line card determines determining a closest edge of the first system clock signal to a transition of the SYNC input signal and determines a time difference between the closest edge of the first system clock signal and a transition of the SYNC feedback. The SYNC output signal is adjusted based on the time difference using a coarse adjustment by adjusting a divide ratio of the divider circuit and using a fine adjustment in the PLL based on a residue of a remainder of the time difference not accounted for by the coarse time adjustment.