A method for synchronizing a signal having modulated chirps. The modulation corresponds to circular permutation of the pattern of variation in the instantaneous frequency of a chirp over the symbol time. For a portion of the signal that is representative of at least one chirp, estimating a first piece of time synchronization information representative of a time shift in the signal relative to a given time reference. Using the first piece of time synchronization information, a piece of fractional frequency synchronization information is estimated, that is representative of a frequency shift in the signal relative to a given frequency reference modulo the inverse of the symbol time. Using the piece of fractional frequency synchronization information, second time synchronization information is estimated, representative of a time shift in the signal relative to the given time reference.

A method for synchronizing a signal having modulated chirps. The modulation corresponds to circular permutation of the pattern of variation in the instantaneous frequency of a chirp over the symbol time. For a portion of the signal that is representative of at least one chirp, estimating a first piece of time synchronization information representative of a time shift in the signal relative to a given time reference. Using the first piece of time synchronization information, a piece of fractional frequency synchronization information is estimated, that is representative of a frequency shift in the signal relative to a given frequency reference modulo the inverse of the symbol time. Using the piece of fractional frequency synchronization information, second time synchronization information is estimated, representative of a time shift in the signal relative to the given time reference.

A low voltage drive circuit includes a transmit digital to analog circuit that converts transmit digital data into analog outbound data by: generating a DC component; generating a first oscillation at a first frequency; generating a second oscillation at the first frequency; and outputting the first oscillation or the second oscillation on a bit-by-bit basis in accordance with the transmit digital data to produce an oscillating component, wherein the DC component is combined with the oscillating component to produce the analog outbound data, and wherein the oscillating component and the DC component are combined to produce the analog outbound data. A drive sense circuit drives an analog transmit signal onto a bus, wherein the analog outbound data is represented within the analog transmit signal as variances in loading of the bus at the first frequency and wherein analog inbound data is represented within an analog receive signal as variances in loading of the bus at a second frequency.

A low voltage drive circuit includes a transmit digital to analog circuit that converts transmit digital data into analog outbound data by: generating a DC component; generating a first oscillation at a first frequency; generating a second oscillation at the first frequency; and outputting the first oscillation or the second oscillation on a bit-by-bit basis in accordance with the transmit digital data to produce an oscillating component, wherein the DC component is combined with the oscillating component to produce the analog outbound data, and wherein the oscillating component and the DC component are combined to produce the analog outbound data. A drive sense circuit drives an analog transmit signal onto a bus, wherein the analog outbound data is represented within the analog transmit signal as variances in loading of the bus at the first frequency and wherein analog inbound data is represented within an analog receive signal as variances in loading of the bus at a second frequency.

The present disclosure discloses a clock and data recovery circuit. The clock and data recovery circuit may include a clock recovery unit configured to output a recovery clock signal by operating a first time-to-digital conversion circuit or a second time-to-digital conversion circuit depending on a phase difference between a clock of an input signal and the recovery clock signal, and a data recovery unit configured to sample data from the input signal and output recovery data.

The present disclosure discloses a clock and data recovery circuit. The clock and data recovery circuit may include a clock recovery unit configured to output a recovery clock signal by operating a first time-to-digital conversion circuit or a second time-to-digital conversion circuit depending on a phase difference between a clock of an input signal and the recovery clock signal, and a data recovery unit configured to sample data from the input signal and output recovery data.

An equalizing circuit includes a first current summer that receives a data signal and a first plurality of feedback signals, a first multiplexer that selects a first sampling clock signal from a plurality of clock signals using a signal that indicates a mode of operation of the equalizing circuit, and a first slicer that samples the output of the first current summer in accordance with timing provided by the first sampling clock signal. The equalizing circuit can have a second current summer that receives the data signal and a second plurality of feedback signals, a second multiplexer that selects a second sampling clock signal from the plurality of clock signals using the signal that indicates the mode of operation of the equalizing circuit, and a second slicer that samples the output of the second current summer according to timing provided by the second sampling clock signal.

An equalizing circuit includes a first current summer that receives a data signal and a first plurality of feedback signals, a first multiplexer that selects a first sampling clock signal from a plurality of clock signals using a signal that indicates a mode of operation of the equalizing circuit, and a first slicer that samples the output of the first current summer in accordance with timing provided by the first sampling clock signal. The equalizing circuit can have a second current summer that receives the data signal and a second plurality of feedback signals, a second multiplexer that selects a second sampling clock signal from the plurality of clock signals using the signal that indicates the mode of operation of the equalizing circuit, and a second slicer that samples the output of the second current summer according to timing provided by the second sampling clock signal.

System and method of timing recovery for recovering a clock signal with reduced interaction between an adaptive channel estimator and the overall timing loop for correcting clock phase. The channel response estimation in the timing recovery loop is dynamically adapted to the current channel response that varies over time. The channel estimator includes compensation logic operable to detect and compensate a correction of clock phase ascribed to the channel estimator. The compensation logic can calculate the offset between a center of filter (COF) value and a COF nominal value, the offset indicative of the amount and direction of clock phase correction contributed by the channel estimator. Based on the offset, the compensation logic adjusts the estimates channel response by adjusting the tap weights of the channel estimator to correct the offset, thereby compensating the clock phase correction.

A global navigation satellite system (“GNSS”) positioning method is provided, based upon a GNSS radio signal that comprises a navigation message transmitted as a succession of data packets. Each data packet is present in the GNSS radio signal as a sequence of symbols obtained by application of a code preceded by a synchronization symbol header. The data packets are organized internally into data fields. At least certain data packets of the succession of data packets contain a synchronization bit field translated by application of the code into a synchronization symbol pattern.