A method for processing user interaction information by an electronic device, includes: executing an application in an unsecure area of the electronic device; instantiating an object of the application; recognizing a user interface of the application, converting a user reaction between a pseudo-event and the instantiated object into data, and transmitting the data to a secure area of the electronic device; mirroring the application to the secure area by using the data; based on a user input being detected, inferring an event to be recognized by a graphical user interface (GUI) framework of the electronic device; and interpreting, in the secure area, the user reaction to the instantiated object corresponding to the inferred event

A computer-implemented method, computer program product and computing system for: processing an unencoded data file to identify a plurality of file segments, wherein the unencoded data file is a dataset for use with a blockchain process; mapping each of the plurality of file segments to a portion of a dictionary file to generate a plurality of mappings that each include a starting location and a length, thus generating a related encoded data file based, at least in part, upon the plurality of mappings; receiving a request to manipulate the unencoded data file from the blockchain process; and processing the related encoded data file based, at least in part, upon the plurality of mappings and the dictionary file to generate a modified encoded data file that represents the requested manipulations of the unencoded data file.

A field-programmable gate array (FPGA) cluster, comprising a plurality of FPGA devices, can be used to accelerate homomorphic encryption functionality. In particular, the FPGA cluster can accelerate the relinearization process used in homomorphic encryption by using multiple FPGA devices to perform portions of the relinearization process in parallel. Further, the use of the FPGA cluster provides sufficient memory resources to allow data used by the relinearization process, namely the keyswitch keys, to be stored on-chip.

A low latency relinearization process can be performed in an FPGA cluster for accelerating homomorphic encryption. The low-latency process performs an early calculation of matrix rows to make the summation result available earlier in the relinearization to reduce waiting of subsequent operations.

In response to identifying that a Single Instruction, Multiple Data (SIMD) operation has been instructed to be performed or has been performed by a Fully-Homomorphic Encryption (FHE) software on one or more original ciphertexts, performing the following steps: Performing the same operation on one or more original plaintexts, respectively, that are each a decrypted version of one of the one or more original ciphertexts. Decrypting a ciphertext resulting from the operation performed on the one or more original ciphertexts. Comparing the decrypted ciphertext with a plaintext resulting from the same operation performed on the one or more original plaintexts. Based on said comparison, performing at least one of: (a) determining an amount of noise caused by the operation, (b) determining whether unencrypted data underlying the one or more original ciphertexts has become corrupt by the operation, and (c) determining correctness of an algorithm which includes the operation.

A data market system located at the Internet includes a storage circuit, an input surface circuit, and a processor. The input surface circuit is used for receiving a query and an encrypted data packet. The processor is used for controlling the input surface circuit to receive the encrypted data packet and to store the encrypted data packet in the storage circuit. The processor processes the encrypted data packet according to the query. The encrypted data packet corresponds to at least one of anonymization application programming interface, blockchain, differential privacy, and homomorphic encryption provided by the data market system.

Systems and methods for configuring a reduced instruction set computer processor architecture to execute fully homomorphic encryption (FHE) logic gates as a streaming topology. The method includes parsing sequential FHE logic gate code, transforming the FHE logic gate code into a set of code modules that each have in input and an output that is a function of the input and which do not pass control to other functions, creating a node wrapper around each code module, configuring at least one of the primary processing cores to implement the logic element equivalents of each element in a manner which operates in a streaming mode wherein data streams out of corresponding arithmetic logic units into the main memory and other ones of the plurality arithmetic logic units.

A first component determines encrypted data representing an event and encrypted threshold data corresponding to an outlier of the event. The first system may process the data using, for example, one or more composite integers, and may send the result to a second system. This second system may subtract the data to determine of the encrypted data is greater than, less than, or equal to the encrypted threshold. If so, the second system may determine that the encrypted data corresponds to an outlier of the data. The second system may send an indication of this determination to a third system.

Disclosed is an electronic apparatus. The electronic apparatus includes a memory storing a composite function in which at least two polynomials are composed and a processor configured to, based on a comparison operation command being received for a plurality of homomorphic ciphertexts, perform operation by reflecting the plurality of homomorphic ciphertexts to the composite function, and obtain a comparison result of the plurality of homomorphic ciphertexts based on the operation result, each of the at least two polynomials may output a value in a preset range for a value in a preset domain, and a domain of one of the at least two polynomials may be determined based on a range of a previous polynomial.

A system and method for training a decision tree are disclosed. A method includes publishing, by a first party, a first set of nominated cut-off values at a current node of a decision tree to be trained, computing a first respective impurity value for the first set of nominated cut-off values at the current node, creating first respective n shares of the first respective impurity value, transmitting, from the first party and so a second party, one of the first respective n shares of the first respective impurity value, receiving from the second party one of a second respective n shares of the second respective impurity value, adding a group of impurity values to yield a combined impurity value based on the one of the first respective n shares and the one of the second respective n shares and determining, based on the combined impurity value, a best threshold.