A communication system includes a first system input adapted to be coupled to a DC transient current transitioning between a starting level and a target level on a pseudo-sinusoidal path and incudes a second system input adapted to be coupled to a HART signal. The system includes an adder circuit having an output, a first adder input coupled to the first system input and a second adder input coupled to the second system input. The adder circuit provides a superimposed signal comprising the HART signal and the DC transient current.

An Ethernet transceiver is disclosed. The Ethernet transceiver includes transceiver circuitry to couple to one end of an Ethernet link. The transceiver circuitry includes transmit circuitry to transmit high-speed Ethernet data along the Ethernet link at a first data rate and receiver circuitry. The receiver circuitry includes adaptive filter circuitry and correlator circuitry. The receiver circuitry is responsive to an inline signal to operate in a low-power alert mode with the adaptive filter circuitry disabled and to receive alert signals from the Ethernet link simultaneous with transmission of the Ethernet data by the transmit circuitry. The alert signals are detected by the correlator circuitry and include a sequence of alert intervals exhibiting encoded data at a second data rate less than the first data rate.

An Ethernet transceiver is disclosed. The Ethernet transceiver includes transceiver circuitry to couple to one end of an Ethernet link. The transceiver circuitry includes transmit circuitry to transmit high-speed Ethernet data along the Ethernet link at a first data rate and receiver circuitry. The receiver circuitry includes adaptive filter circuitry and correlator circuitry. The receiver circuitry is responsive to an inline signal to operate in a low-power alert mode with the adaptive filter circuitry disabled and to receive alert signals from the Ethernet link simultaneous with transmission of the Ethernet data by the transmit circuitry. The alert signals are detected by the correlator circuitry and include a sequence of alert intervals exhibiting encoded data at a second data rate less than the first data rate.

Various examples of systems and methods are provided for slide processing. In one example, among others, a system for processing microscope slides includes a slide positioner that can adjust a position of a slide and a slide treatment system that can dispense a micro stream of a fluid at a location on the slide when the slide is positioned beneath a jet nozzle of the slide treatment system. The system can include a slide sled that can align a smearing slide with a surface of the slide including a fluid sample is disposed, and support the smearing slide at a predefined angle with respect to the surface of the slide. In another example, a method includes obtaining a slide including a sample disposed on a surface, positioning the slide below to a jet nozzle, and dispensing a micro stream of a fluid onto the sample using the jet nozzle.

A communication system includes a first system input adapted to be coupled to a DC transient current transitioning between a starting level and a target level on a pseudo-sinusoidal path and incudes a second system input adapted to be coupled to a HART signal. The system includes an adder circuit having an output, a first adder input coupled to the first system input and a second adder input coupled to the second system input. The adder circuit provides a superimposed signal comprising the HART signal and the DC transient current.

A communication system includes a first system input adapted to be coupled to a DC transient current transitioning between a starting level and a target level on a pseudo-sinusoidal path and incudes a second system input adapted to be coupled to a HART signal. The system includes an adder circuit having an output, a first adder input coupled to the first system input and a second adder input coupled to the second system input. The adder circuit provides a superimposed signal comprising the HART signal and the DC transient current.

An Ethernet transceiver is disclosed. The Ethernet transceiver includes transceiver circuitry to couple to one end of an Ethernet link. The transceiver circuitry includes transmit circuitry to transmit high-speed Ethernet data along the Ethernet link at a first data rate and receiver circuitry. The receiver circuitry includes adaptive filter circuitry and correlator circuitry. The receiver circuitry is responsive to an inline signal to operate in a low-power alert mode with the adaptive filter circuitry disabled and to receive alert signals from the Ethernet link simultaneous with transmission of the Ethernet data by the transmit circuitry. The alert signals are detected by the correlator circuitry and include a sequence of alert intervals exhibiting encoded data at a second data rate less than the first data rate.

An Ethernet transceiver is disclosed. The Ethernet transceiver includes transceiver circuitry to couple to one end of an Ethernet link. The transceiver circuitry includes transmit circuitry to transmit high-speed Ethernet data along the Ethernet link at a first data rate and receiver circuitry. The receiver circuitry includes adaptive filter circuitry and correlator circuitry. The receiver circuitry is responsive to an inline signal to operate in a low-power alert mode with the adaptive filter circuitry disabled and to receive alert signals from the Ethernet link simultaneous with transmission of the Ethernet data by the transmit circuitry. The alert signals are detected by the correlator circuitry and include a sequence of alert intervals exhibiting encoded data at a second data rate less than the first data rate.

A network interface controller including a data alignment module, a boundary determination module and a checksum module is provided. The data alignment module receives raw data and re-combines the raw data as first valid data, wherein the raw data includes a first layer protocol segment and a second layer protocol segment. The boundary determination module receives the raw data in parallel to the data alignment module and performs a boundary determination operation on the raw data to generate a boundary information indicating a boundary between the first layer protocol segment and the second layer protocol segment. The checksum module is coupled to the data alignment module and configured to disassemble the first valid data as second valid data and calculate a checksum according to the boundary information and the second valid data.

A network interface controller including a data alignment module, a boundary determination module and a checksum module is provided. The data alignment module receives raw data and re-combines the raw data as first valid data, wherein the raw data includes a first layer protocol segment and a second layer protocol segment. The boundary determination module receives the raw data in parallel to the data alignment module and performs a boundary determination operation on the raw data to generate a boundary information indicating a boundary between the first layer protocol segment and the second layer protocol segment. The checksum module is coupled to the data alignment module and configured to disassemble the first valid data as second valid data and calculate a checksum according to the boundary information and the second valid data.