Patent classifications
H04L27/0014
Phase noise reference signal transmission techniques
Provided is a reference signal transmission method and device. The method includes that a base station transmits indication information to a UE through a downlink control signaling or a higher layer signaling, where the indication information includes one of: information indicating that the UE transmits a reference signal, information indicating whether the reference signal is contained in a physical downlink shared channel or a physical downlink control channel, or information indicating a transmission mode of a downlink reference signal or an uplink reference signal; or the base station pre-defines with the UE a time-frequency resource or a parameter set required by the UE or the base station to transmit the reference signal, where the time-frequency resource or the parameter set includes at least one of: a time domain symbol position, a frequency domain position, a transmission period and a subframe offset, a type of a reference signal sequence or an orthogonal mask. This solves the problem in the existing art of how to properly place a reference signal on time-frequency resources and trigger a signaling correspondingly.
PLATFORM FOR FACILITATING DEVELOPMENT OF INTELLIGENCE IN INDUSTRIAL INTERNET OF THINGS WITH ADAPTIVE EDGE COMPUTE MANAGEMENT SYSTEM
A platform for facilitating development of intelligence in an Industrial Internet of Things (IIoT) system generally includes a plurality of distinct data-handling layers having an industrial monitoring systems layer that collects data from or about a plurality of industrial entities in an industrial environment; an industrial entity-oriented data storage systems layer that stores the data collected by the industrial monitoring systems layer; and an adaptive intelligent systems layer that facilitates the coordinated development and deployment of intelligent systems in the IIoT system; wherein the adaptive intelligent systems layer includes an adaptive edge compute management system that adaptively manages edge computation, storage, and processing in the IIoT system.
TRANSCEIVER
A transceiver configured to: determine a reference frequency offset relative to a second transceiver based on double sided ranging; correct first and second portions of a packet received from a respective first and second antenna; and determine an angle of arrival of the packet based on corrected first and second portions and the reference frequency offset.
[FIG. 10]
DATA TRANSMISSION DEVICE, METHOD, AND SYSTEM
Embodiments of the present invention relate to the communications field and disclose a data transmission device, method, and system, so as to better improve an average downlink throughput of UE. A specific solution is: A determining unit determines a downlink frequency shift according to a received uplink signal sent by a terminal device, and determines a second transmit frequency according to the downlink frequency shift and a first transmit frequency; and a sending unit sends a downlink signal to the terminal device according to the second transmit frequency determined by the determining unit, so that the terminal device receives the downlink signal according to a receive frequency corresponding to the first transmit frequency, where the downlink signal includes at least one of a DMRS or downlink data. The present invention is applied in a data transmission process.
USE OF FREQUENCY OFFSET INFORMATION FOR WIRELESS NETWORKS
A technique includes receiving, by a user device from a base station in a wireless network, a frequency offset information (FOI), adjusting, by the user device, an uplink transmit frequency based on the frequency offset information, and transmitting, by the user device, at least one of data and control information to the base station based on the adjusted uplink transmit frequency.
RECEIVING CIRCUIT CAPABLE OF PERFORMING I/Q MISMATCH CALIBRATION BASED ON EXTERNAL OSCILLATING SIGNAL
A receiving circuit includes: a first receiving terminal for receiving a RF signal; a second receiving terminal for receiving an external oscillating signal generated by an external oscillator; a low-noise amplifier coupled with the first receiving terminal and the second receiving terminal and utilized for generating an output signal; a first switch element positioned between the second receiving terminal and the low-noise amplifier; an in-phase signal processing circuit for generating an in-phase detection signal based on the output signal; an quadrature signal processing circuit for generating an quadrature detection signal based on the output signal; and a calibration circuit for controlling the first switch element and capable of performing an I/Q mismatch calibration operation according to the in-phase detection signal and the quadrature detection signal when the first switch element is turned on.
Carrier frequency offset estimation for wireless communication
Methods and system for carrier frequency offset (CFO) estimation are described. The method includes determining correlation values between a plurality of samples from a received signal and a plurality of reference signals corresponding to a plurality of CFO candidates. A set of correlation values which exceeds a threshold is determined and a corresponding CFO candidate for each correlation value in the set is selected. A CFO estimate based on an interpolation of selected CFO candidates is then calculated.
HIGH SPEED PULSE MODULATION SYSTEM
A modulator operable to control an oscillator is described. The modulator can include a memory that stores oscillator control values and a bit streaming block. The bit streaming block can generate a bit stream based on the oscillator control values and transmit the bit stream to the oscillator to control an oscillation frequency of the oscillator. The modulator can also include a bit streaming loader (BSL). The BSL can receive one or more of the oscillator control values from the memory, generate one or more corresponding bit values based on the one or more of the oscillator control values, and provide the one or more bit values to the bit streaming block. The bit streaming block can then generate the bit stream based the one or more bit values generated by the BSL.
ANALOG FRACTIONAL-N PHASE-LOCKED LOOP
An analog fractional-N phase-locked loop includes an oscillator loop having a reference input, a feedback input, and a loop output, and a fractional feedback divider configured to divide signals on the loop output by a divisor. Output of the fractional feedback divider is fed back to the feedback input. A compensation circuit is coupled to, and configured to apply a time delay to, the reference input or the feedback input, to compensate for delay introduced by the fractional feedback divider. The compensation circuit may be a digital-to-time converter configured to convert a digital delay signal into the time delay. The digital-to-time converter may be coupled to the reference input to delay signals to match feedback delay introduced by the fractional feedback divider, or to the feedback input to subtract the time delay to cancel feedback delay introduced by the fractional feedback divider.
RECEIVER WITH COHERENT MATCHED FILTER
In one implementation, a receiver has a module to calculate the cross-correlation between a portion of a digital representation of a received signal and a reference signal. The receiver also has a module to generate an estimate of a portion of a message potentially included in the digital representation of the received signal and a screening module to determine the likelihood that the received signal includes a message. For a received signal that is determined likely to include a message, the receiver includes a carrier refinement module to shift the frequency of carrier pulses in the digital representation of the received signal toward a desired frequency and to align the phase of carrier pulses in the digital representation of the received signal with a desired phase and a coherent matched filter to recover the message from the digital representation of the received signal.