A transmitter in a wireless communication network comprises a Carrier Interferometry (CI) coder and a multicarrier modulator communicatively coupled to the CI coder. The CI coder encodes a plurality of data symbols with a plurality of CI codes to produce a plurality of CI symbol values, wherein each of the plurality of CI symbol values equals a sum of information-modulated CI code chips. Each information-modulated CI code chip equals a CI code chip multiplied by one of the plurality of data symbols. The modulator modulates each CI symbol value onto a different subcarrier frequency to produce a multicarrier signal.

A CTLE-based SERDES receiver circuit using ISI metering provides an improved SERDES I/O performance. The CTLE SERDES receiver circuit may include an analog receiver frontend to generate an analog-to-digital converter (ADC) digital signal and a reduced ISI signal, a data path circuit to generate a sliced data stream and sliced cursor error stream, a digital signal processing (DSP) circuit to generate a converged data stream, a multi-tap intersymbol interference (ISI) assessment circuit to generate a weighted ISI sum, and an ISI minimization circuit to generate a continuous time linear equalizer (CTLE) adaptation control signal based on the weighted ISI sum.

A CTLE-based SERDES receiver circuit using ISI metering provides an improved SERDES I/O performance. The CTLE SERDES receiver circuit may include an analog receiver frontend to generate an analog-to-digital converter (ADC) digital signal and a reduced ISI signal, a data path circuit to generate a sliced data stream and sliced cursor error stream, a digital signal processing (DSP) circuit to generate a converged data stream, a multi-tap intersymbol interference (ISI) assessment circuit to generate a weighted ISI sum, and an ISI minimization circuit to generate a continuous time linear equalizer (CTLE) adaptation control signal based on the weighted ISI sum.

A cable equalizer configured as part of a cable comprising a first stage, a second stage, and a third stage. The first stage comprises a first stage bias current circuit configured to generate a bias current and a pre-emphasis module configured to introduce pre-emphasis into a received signal to counter the effects of signal amplification. Also part of the first stage is a bias voltage circuit configured to provide a bias voltage to the first stage. The second stage comprises a buffer configured impedance match the first stage. The third stage comprises a third stage bias current circuit configured to generate a bias current and a tank equalizer circuit configured to perform frequency specific equalization on a second stage signal. An amplifier is configured to amplify the second stage signal to create an amplified signal, which is output from the cable equalizer by an output driver.

An equalization method has been developed for low latency, low bandwidth wireless communication channel environments. With this method, an exact copy, nearly exact copy, or some facsimile of a message (or associated information), which was transmitted via a low latency, low bandwidth wireless communication channel, is also sent via a backend communication channel such as a fiber optic network. Equalization is generally performed by comparing the originally received message to the copy sent via the backend channel. The original message can incorporate an added channel delay to compensate for the time delay between the primary wireless channel and the backend channel.

An equalization method has been developed for low latency, low bandwidth wireless communication channel environments. With this method, an exact copy, nearly exact copy, or some facsimile of a message (or associated information), which was transmitted via a low latency, low bandwidth wireless communication channel, is also sent via a backend communication channel such as a fiber optic network. Equalization is generally performed by comparing the originally received message to the copy sent via the backend channel. The original message can incorporate an added channel delay to compensate for the time delay between the primary wireless channel and the backend channel.

A method and a device for transmitting an A-PPDU in a wireless LAN system are proposed. Specifically, a transmission STA generates an A-PPDU and transmits the A-PPDU to a reception STA. A first PPDU and a second PPDU are aggregated into the A-PPDU. The first PPDU includes an L-Header field, a first EDMG-Header field, and a first data field. The second PPDU includes a second EDMG-Header field and a second data field. Zero padding is inserted in the first data field on the basis of the minimum number of symbol blocks of the first PPDU.

Some examples described herein provide for an integrated circuit including a continuous time linear equalizer (CTLE) circuit and a method of operating the integrated circuit. In an example, an integrated circuit includes a transconductance amplifier stage and a transimpedance amplifier stage. The transconductance amplifier stage has a first input node and a first output node. The transconductance amplifier stage includes a first complementary device inverter. The transimpedance amplifier stage has a second input node and a second output node. The first output node is electrically connected to the second input node. The transimpedance amplifier stage includes a second complementary device inverter.

Some examples described herein provide for an integrated circuit including a continuous time linear equalizer (CTLE) circuit and a method of operating the integrated circuit. In an example, an integrated circuit includes a transconductance amplifier stage and a transimpedance amplifier stage. The transconductance amplifier stage has a first input node and a first output node. The transconductance amplifier stage includes a first complementary device inverter. The transimpedance amplifier stage has a second input node and a second output node. The first output node is electrically connected to the second input node. The transimpedance amplifier stage includes a second complementary device inverter.

In an information processing device, a communication control unit performs communication using a first communication method and using a second communication method that is faster than the first communication method. An equalizing unit performs an equalization operation using the first communication method with respect to a first information processing device in a redundancy system in which redundancy is achieved between the first information processing device and a second information processing device using the first communication method. After the equalization operation is completed by the equalizing unit, another equalizing unit performs the equalization operation using the second communication method with respect to a third information processing device, and builds a redundancy system in which the concerned information processing device and the third information processing device are used.