A hardware system for simulating a network physical layer for communication channels. The hardware system includes a plurality of hardware processors configurable to model a network physical layer and communication channels. The hardware system is further implemented where the hardware processors are configured such that a single set of hardware, including a single set of gates and registers, is used in a single simulation to model a plurality of virtual routers for different nodes.

With the advent of manycore architecture, on-chip interconnect connects a number of cores, caches, memory modules, accelerators, graphic processing unit (GPU) or chiplets in one system. However, on-chip interconnect architecture consumes a significant portion of total parallel computing chip power. Power-gating is an effective technique to reduce power consumption by powering off the routers, but it suffers from a large wake-up latency to resume the full activity of routers. Recent research aims to improve the wake-up latency penalty by hiding it through early wake-up techniques. However, these techniques do not exploit the full advantage of power-gating due to the early wake-up. Consequently, they do not achieve significant power savings. The present invention provides a new router architecture that remedies the large wake-up latency overheads while providing significant power savings. The invention takes advantage of a simple switch to transmit packets without waking up the router. Additionally, the technique hides the wake-up latency by continuing to provide packet transmission during the wake-up phase.

With the advent of manycore architecture, on-chip interconnect connects a number of cores, caches, memory modules, accelerators, graphic processing unit (GPU) or chiplets in one system. However, on-chip interconnect architecture consumes a significant portion of total parallel computing chip power. Power-gating is an effective technique to reduce power consumption by powering off the routers, but it suffers from a large wake-up latency to resume the full activity of routers. Recent research aims to improve the wake-up latency penalty by hiding it through early wake-up techniques. However, these techniques do not exploit the full advantage of power-gating due to the early wake-up. Consequently, they do not achieve significant power savings. The present invention provides a new router architecture that remedies the large wake-up latency overheads while providing significant power savings. The invention takes advantage of a simple switch to transmit packets without waking up the router. Additionally, the technique hides the wake-up latency by continuing to provide packet transmission during the wake-up phase.

A system provisions global logical entities that facilitate the operation of logical networks that span two or more datacenters. These global logical entities include global logical switches that provide L2 switching as well as global routers that provide L3 routing among network nodes in multiple datacenters. The global logical entities operate along side local logical entities that are for operating logical networks that are local within a datacenter.

A system provisions global logical entities that facilitate the operation of logical networks that span two or more datacenters. These global logical entities include global logical switches that provide L2 switching as well as global routers that provide L3 routing among network nodes in multiple datacenters. The global logical entities operate along side local logical entities that are for operating logical networks that are local within a datacenter.

Various example embodiments for supporting multicast are presented. Various example embodiments for supporting multicast are configured to support multicast, on a multicast tree for a multicast group, based on use of penultimate hop popping (PHP) on the multicast tree. Various example embodiments for supporting multicast are configured to support multicast, on a multicast tree for a multicast group, based on use of PHP on the multicast tree where the multicast tree is Point-to-Multipoint (P2MP) Multiprotocol Label Switching (MPLS) tree that is formed based on a TREE-SID multicast solution (although it will be appreciated that PHP may be applied on other types of multicast trees (e.g., other than P2MP MPLS multicast trees), on multicast trees formed based on other multicast solutions (e.g., other than TREE-SID), or the like, as well as various combinations thereof).

Various example embodiments for supporting multicast are presented. Various example embodiments for supporting multicast are configured to support multicast, on a multicast tree for a multicast group, based on use of penultimate hop popping (PHP) on the multicast tree. Various example embodiments for supporting multicast are configured to support multicast, on a multicast tree for a multicast group, based on use of PHP on the multicast tree where the multicast tree is Point-to-Multipoint (P2MP) Multiprotocol Label Switching (MPLS) tree that is formed based on a TREE-SID multicast solution (although it will be appreciated that PHP may be applied on other types of multicast trees (e.g., other than P2MP MPLS multicast trees), on multicast trees formed based on other multicast solutions (e.g., other than TREE-SID), or the like, as well as various combinations thereof).

An interconnection network for a processing unit having an array of cores. The interconnection network includes routers and adaptable links that selectively connect routers in the interconnection network. For example, each router may be electrically connected to one or more of the adaptable links via one or more multiplexers and a link controller may control the multiplexers to selectively connect routers via the adaptable links. In another example, adaptable links may be formed as part of an interposer and the link controller selectively connect routers via the adaptable links in the interposer using interposer switches. The adaptable links enable the interconnection network to be dynamically partitioned. Each of those partitions may be dynamically reconfigured to form a topology.

An interconnection network for a processing unit having an array of cores. The interconnection network includes routers and adaptable links that selectively connect routers in the interconnection network. For example, each router may be electrically connected to one or more of the adaptable links via one or more multiplexers and a link controller may control the multiplexers to selectively connect routers via the adaptable links. In another example, adaptable links may be formed as part of an interposer and the link controller selectively connect routers via the adaptable links in the interposer using interposer switches. The adaptable links enable the interconnection network to be dynamically partitioned. Each of those partitions may be dynamically reconfigured to form a topology.

At a router, at least one memory and computer program code stored therein are configured to, with at least one processor, cause the router to: determine source router identification information for a tunnel traversing the router based on a routable source IP address for the tunnel; determine destination router identification information for the tunnel based on a routable destination IP address for the tunnel; program a bit string entry for the tunnel in a Bit Index Forwarding Table (BIFT) for tunnels from a source router to a plurality of destination routers, the BIFT being indexed based on the source router identification information and at least a portion of the destination router identification information; and route packet data received at the router according to the BIFT.