A storage system determines source addresses, and destination addresses in a storage system, for network traffic. The storage system determines a hash algorithm, from a plurality of hash algorithms. The hash algorithm is to be used across the source addresses for load-balancing the network traffic to the destination addresses. The storage system determines that the hash algorithm more closely meets one or more load-balancing criteria than at least one other hash algorithm, of the plurality of hash algorithms. The storage system distributes the network traffic from the source addresses to the destination addresses in the storage system, with load-balancing according to the determined hash algorithm.

Examples include techniques for virtual Ethernet switching of a multi-node fabric. In some examples, first Ethernet links coupled with a group of Ethernet gateways are link aggregated. The group of Ethernet gateways couple with respective individual physical switch ports of a fabric switch of a multi-node fabric to form a default logical gateway to provide an uplink between a virtual Ethernet switch and an Ethernet network external to the multi-node fabric. Also, one or more individual Ethernet gateways coupled with respective individual physical switch ports of the fabric switch may be arranged to provide one or more respective downlinks between the virtual Ethernet switch and one or more Ethernet nodes external to the multi-node fabric via respective second Ethernet links coupled with the one or more individual Ethernet gateways.

The subject matter disclosed herein relates to a frame switch of an AFDX network in which the data acquisition application is decentralized. When the switch has to acquire the data transmitted on a virtual link, the switching table contains, apart from the input port and the output port (s) taken by this link, an ID representing the MAC address of the switch. The frames of this link are then not only switched but also transmitted to the network interface of the switch and processed by a dedicated application (DDA), hosted inside the switch. This application can be interrogated by a remote server and transfer the data that it has stored locally.

Present invention disclose a hardware accelerator and a chip, and the hardware accelerator includes: an interface circuit and an accelerator core coupled to the interface circuit, where the interface circuit is configured to receive a first task request, perform decoding on the first task request to acquire identifier information, and configure, according to the identifier information, the first task request to be in an FIFO queue that matches the identifier information; a scheduling controller is configured to determine, from at least two channel groups, one or more target channel groups that have at least one to-be-processed second task request in an n.sup.th period, receive a time parameter that is fed back by the accelerator core and corresponding to the target channel group, and schedule the at least one second task request in the one or more target channel groups according to the time parameter and a weighted round robin algorithm.

Methods, systems, and apparatus, including computer programs encoded on computer-storage media, for connecting processors using twisted torus configurations. In some implementations, a cluster of processing nodes is coupled using a reconfigurable interconnect fabric. The system determines a number of processing nodes to allocate as a network within the cluster and a topology for the network. The system selects an interconnection scheme for the network, where the interconnection scheme is selected from a group that includes at least a torus interconnection scheme and a twisted torus interconnection scheme. The system allocates the determined number of processing nodes of the cluster in the determined topology, sets the reconfigurable interconnect fabric to provide the selected interconnection scheme for the processing nodes in the network, and provides access to the network for performing a computing task.

Methods, systems, and apparatus, including computer programs encoded on computer-storage media, for connecting processors using twisted torus configurations. In some implementations, a cluster of processing nodes is coupled using a reconfigurable interconnect fabric. The system determines a number of processing nodes to allocate as a network within the cluster and a topology for the network. The system selects an interconnection scheme for the network, where the interconnection scheme is selected from a group that includes at least a torus interconnection scheme and a twisted torus interconnection scheme. The system allocates the determined number of processing nodes of the cluster in the determined topology, sets the reconfigurable interconnect fabric to provide the selected interconnection scheme for the processing nodes in the network, and provides access to the network for performing a computing task.

Switching hubs includes switches in a hierarchy type communication network used in a vehicle, the switches respectively include a first section storing a received Identification (ID) number received by one port in a memory as an identifier of the respective switches, and a second section sending a port-specific identifier from each of the other ports in the respective switches by generating the port-specific identifier as a combination of a port number and the received ID number according to a preset rule, thereby enabling a dynamic assignment of an identifier to each of the switches in the communication network.

A storage system is provided. The storage system includes a plurality of storage units, each having a controller and solid-state storage memory. The storage system further includes one or more first pathways that couple processing devices of a plurality of storage nodes and is configured to couple to a network external to the storage system and one or more second pathways that couple the plurality of storage nodes to the plurality of storage units, wherein the one or more second pathways enable multiprocessing applications.

A storage system is provided. The storage system includes a plurality of storage units, each having a controller and solid-state storage memory. The storage system further includes one or more first pathways that couple processing devices of a plurality of storage nodes and is configured to couple to a network external to the storage system and one or more second pathways that couple the plurality of storage nodes to the plurality of storage units, wherein the one or more second pathways enable multiprocessing applications.

One embodiment of the present invention provides a switching system. The switching system includes a plurality of line cards, each of which includes one or more ports, a processor, one or more switch fabric cards for facilitating switching among the line cards, and a memory storing instructions for facilitating efficient hot-swapping. During operation, the switching system identifies a hot-swapping event of a first switch fabric card based on a data structure indicating the one or more switch fabric cards. The hot-swapping event indicates insertion or removal of the first switch fabric card while the switching system remains in an operational state. The switching system then determines an event type associated with the hot-swapping event and manages the first switch fabric card based on the determined event type.