H04L49/15

LINK MONITOR FOR A SWITCH HAVING A PCIE-COMPLIANT INTERFACE, AND RELATED SYSTEMS, DEVICES, AND METHODS
20220400089 · 2022-12-15 ·

Some embodiments relate to a link monitor for a switch having a PCIe-compliant interface. Some embodiments relate to an apparatus including a Peripheral Component Interconnect Express (PCIe)-compliant interface provided at a PCIe domain of a switch. The apparatus may also include a link monitor provided at a switching fabric of the switch that supports the PCIe domain of the switch. The link monitor to observe a factor-changing event of a state of a fabric link and obtain a value at least partially responsive to a weight computation, the weight computation for a factor associated with the factor-changing event. Related devices, systems and methods are also disclosed.

TRANSACTION-BASED MESSAGING AND LOGGING INFRASTRUCTURE FOR NETWORKING SYSTEMS AND COMPUTING DEVICES

Devices, methods, and systems that provide transmitting of messages between different units of a multi-unit system in response to instantiated multi-unit transactions. For example, a method may include: identifying, by a first unit of a multi-unit system of computing devices, an event has occurred that triggers initiation of a transaction; generating, by the first unit, a transaction identifier associated with the transaction, the transaction identifier comprising a unit identifier of the first unit and an application identifier of an application associated with the event; and transmitting, from the first unit and to a second unit of the multi-unit system, the transaction identifier as part of an inter-unit message.

Server, server system, and method of increasing network bandwidth of server

A server includes a normal NIC as an NIC having an expansion function, and a virtual patch panel having a transfer function of transferring packets between the normal NIC and an accelerator utilization type NIC, which is implemented by software. The server is configured such that, when a packet is transferred between the normal NIC and the accelerator utilization type NIC via the virtual patch panel, the target function transfers the packet to and from the APLs.

METHOD AND APPARATUS FOR PROCESSING DATA, DEVICE, AND STORAGE MEDIUM
20220377025 · 2022-11-24 ·

The present disclosure provides a method and apparatus for processing data, a device and a storage medium. The method includes receiving and processing data; obtaining a transmission path of the data; transmitting the data to a destination output port of the data according to the transmission path; and processing the data at the destination output port.

Technologies for switching network traffic in a data center

Technologies for switching network traffic include a network switch. The network switch includes one or more processors and communication circuitry coupled to the one or more processors. The communication circuitry is capable of switching network traffic of multiple link layer protocols. Additionally, the network switch includes one or more memory devices storing instructions that, when executed, cause the network switch to receive, with the communication circuitry through an optical connection, network traffic to be forwarded, and determine a link layer protocol of the received network traffic. The instructions additionally cause the network switch to forward the network traffic as a function of the determined link layer protocol. Other embodiments are also described and claimed.

Automatic multi-stage fabric generation for FPGAs
11509605 · 2022-11-22 · ·

Systems and methods to automatically or manually generate various multi-stage pyramid network based fabrics, either partially connected or fully connected, are disclosed by changing different parameters of multi-stage pyramid network including such as number of slices, number of rings, number of stages, number of switches, number of multiplexers, the size of the multiplexers in any switch, connections between stages of rings either between the same numbered stages (same level stages) or different numbered stages, single or multi-drop hop wires, hop wires of different hop lengths, hop wires outgoing to different directions, hop wires incoming from different directions, number of hop wires based on the number and type of inlet and outlet links of large scale sub-integrated circuit blocks. One or more parameters are changed in each iteration so that optimized fabrics are generated, at the end of iterations, to route a given set of benchmarks or designs having a specific connection requirements.

Automatic multi-stage fabric generation for FPGAs
11509605 · 2022-11-22 · ·

Systems and methods to automatically or manually generate various multi-stage pyramid network based fabrics, either partially connected or fully connected, are disclosed by changing different parameters of multi-stage pyramid network including such as number of slices, number of rings, number of stages, number of switches, number of multiplexers, the size of the multiplexers in any switch, connections between stages of rings either between the same numbered stages (same level stages) or different numbered stages, single or multi-drop hop wires, hop wires of different hop lengths, hop wires outgoing to different directions, hop wires incoming from different directions, number of hop wires based on the number and type of inlet and outlet links of large scale sub-integrated circuit blocks. One or more parameters are changed in each iteration so that optimized fabrics are generated, at the end of iterations, to route a given set of benchmarks or designs having a specific connection requirements.

METHOD AND SYSTEM FOR FACILITATING LOSSY DROPPING AND ECN MARKING
20230046350 · 2023-02-16 ·

Methods and systems are provided for performing lossy dropping and ECN marking in a flow-based network. The system can maintain state information of individual packet flows, which can be set up or released dynamically based on injected data. Each flow can be provided with a flow-specific input queue upon arriving at a switch. Packets of a respective flow are acknowledged after reaching the egress point of the network, and the acknowledgement packets are sent back to the ingress point of the flow along the same data path. As a result, each switch can obtain state information of each flow and perform per-flow packet dropping and ECN marking.

Computing system with hardware reconfiguration mechanism and method of operation thereof
11494322 · 2022-11-08 · ·

A method of operation of a computing system includes: providing a first cluster having a first kernel unit for managing a first reconfigurable hardware device; analyzing an application descriptor associated with an application; generating a first bitstream based on the application descriptor for loading the first reconfigurable hardware device, the first bitstream for implementing at least a first portion of the application; and implementing a first fragment with the first bitstream in the first cluster.

Computing system with hardware reconfiguration mechanism and method of operation thereof
11494322 · 2022-11-08 · ·

A method of operation of a computing system includes: providing a first cluster having a first kernel unit for managing a first reconfigurable hardware device; analyzing an application descriptor associated with an application; generating a first bitstream based on the application descriptor for loading the first reconfigurable hardware device, the first bitstream for implementing at least a first portion of the application; and implementing a first fragment with the first bitstream in the first cluster.