H04L49/15

Packet-based and time-multiplexed network-on-chip

An integrated circuit can include a Network-on-Chip (NoC) having a router network with first and second shared physical channels. The NoC includes one or more master bridge circuits (MBCs) coupled to the router network, where each MBC provides a packet-based interface to a master client circuit coupled thereto for initiating transactions over the router network. Each MBC sends and receives data for the transactions over the router network as flits of packets according to a schedule. The NoC includes one or more slave bridge circuits (SBCs) coupled to the router network, where each SBC provides a packet-based interface to a slave client circuit coupled thereto to for responding to the transactions over the router network. Each SBC sends and receives the flits over the router network according to the schedule. The flits sent from different client circuits are interleaved using time-multiplexing on the first and second shared physical channels.

Packet-based and time-multiplexed network-on-chip

An integrated circuit can include a Network-on-Chip (NoC) having a router network with first and second shared physical channels. The NoC includes one or more master bridge circuits (MBCs) coupled to the router network, where each MBC provides a packet-based interface to a master client circuit coupled thereto for initiating transactions over the router network. Each MBC sends and receives data for the transactions over the router network as flits of packets according to a schedule. The NoC includes one or more slave bridge circuits (SBCs) coupled to the router network, where each SBC provides a packet-based interface to a slave client circuit coupled thereto to for responding to the transactions over the router network. Each SBC sends and receives the flits over the router network according to the schedule. The flits sent from different client circuits are interleaved using time-multiplexing on the first and second shared physical channels.

Control apparatus and control method

Provided is a control apparatus that controls any one or all of a plurality of slave station apparatuses communicating with a terminal apparatus, a plurality of master station apparatuses that control the slave station apparatuses, and a transfer apparatus that transfers data transmitted and received between the master station apparatuses and the slave station apparatuses, the control apparatus including an information acquisition unit that acquires information regarding traffic of the data transmitted and received between the master station apparatuses and the slave station apparatuses, and a switching control unit that performs, on the basis of the information regarding the traffic acquired by the information acquisition unit, switching-control of an assignment relationship between the master station apparatus and the slave station apparatus and switching-control of a transfer path of data between the master station apparatus and the slave station apparatus.

Control apparatus and control method

Provided is a control apparatus that controls any one or all of a plurality of slave station apparatuses communicating with a terminal apparatus, a plurality of master station apparatuses that control the slave station apparatuses, and a transfer apparatus that transfers data transmitted and received between the master station apparatuses and the slave station apparatuses, the control apparatus including an information acquisition unit that acquires information regarding traffic of the data transmitted and received between the master station apparatuses and the slave station apparatuses, and a switching control unit that performs, on the basis of the information regarding the traffic acquired by the information acquisition unit, switching-control of an assignment relationship between the master station apparatus and the slave station apparatus and switching-control of a transfer path of data between the master station apparatus and the slave station apparatus.

Interconnection network with adaptable router lines for chiplet-based manycore architecture

An interconnection network for a processing unit having an array of cores. The interconnection network includes routers and adaptable links that selectively connect routers in the interconnection network. For example, each router may be electrically connected to one or more of the adaptable links via one or more multiplexers and a link controller may control the multiplexers to selectively connect routers via the adaptable links. In another example, adaptable links may be formed as part of an interposer and the link controller selectively connect routers via the adaptable links in the interposer using interposer switches. The adaptable links enable the interconnection network to be dynamically partitioned. Each of those partitions may be dynamically reconfigured to form a topology.

Interconnection network with adaptable router lines for chiplet-based manycore architecture

An interconnection network for a processing unit having an array of cores. The interconnection network includes routers and adaptable links that selectively connect routers in the interconnection network. For example, each router may be electrically connected to one or more of the adaptable links via one or more multiplexers and a link controller may control the multiplexers to selectively connect routers via the adaptable links. In another example, adaptable links may be formed as part of an interposer and the link controller selectively connect routers via the adaptable links in the interposer using interposer switches. The adaptable links enable the interconnection network to be dynamically partitioned. Each of those partitions may be dynamically reconfigured to form a topology.

System-in-package network processors

This disclosure relates to integrated circuit devices that may include a network processor in a data processing die and an on-package memory in a base die. The data processing die may implement one or more network functionalities that may exchange data with low-latency memory, high capacity in the base die. The data processing die may be programmable fabric, which may be dynamically reconfigured during operation.

System-in-package network processors

This disclosure relates to integrated circuit devices that may include a network processor in a data processing die and an on-package memory in a base die. The data processing die may implement one or more network functionalities that may exchange data with low-latency memory, high capacity in the base die. The data processing die may be programmable fabric, which may be dynamically reconfigured during operation.

Intermediary device for daisy chain and tree configuration in hybrid data/power connection

A plurality of intermediary devices may be interposed in a hybrid data/power connection between a power source and a powered device. In one aspect, the intermediary devices may be connected in series. Such connecting may be referred to as “daisy chaining.” In other aspects, the intermediary devices may be connected in a tree or a mesh. Each intermediary device may be configured to consume, for its own use, power that is supplied over the hybrid data/power connection and to deliver remaining power over the hybrid data/power connection to at least one other device. Furthermore, each intermediary device may be configured to independently route data and power to downstream devices.

Elastic internet protocol (IP) address for hypervisor and virtual router management in a branch environment

An elastic Internet Protocol (IP) address for hypervisor and virtual router management in a branch environment may be provided. First, an IP address may be assigned to a hypervisor associated with a virtual branch. Next, it may be determined that a virtual machine (VM) has been instantiated at the virtual branch. In response to determining that the VM has been instantiated at the virtual branch, the IP address may then be released. It may next be determined that the VM is in a failed state and then, in response to determining that the VM is in the failed state, the IP address may be reassigned to the hypervisor.