PCI Express (PCIE) is a Bus or I/O interconnect standard for use inside the computer or embedded system enabling faster data transfers to and from peripheral devices. The standard has achieved a degree of stability such that other applications can be implemented using PCIE as basis. A PCIE based interconnect scheme for switching and inter-connection between multiple PCIE enabled systems, each having its own PCIE root complexes controlling a PCIE bus, enabling the scalability of PCIE architecture to be used for data transport between inter-connected PCIE buses of systems forming a cluster using PCIE protocol, through a switch enabled for PCIE interconnect, forming the hub of a star connected network is proposed. These systems forming the cluster can be any computing, control, storage or embedded system. The scalability of the interconnect will allow the cluster to grow the bandwidth between the systems as they become necessary without changing to a different connection architecture.

PCI Express (PCIE) is a Bus or I/O interconnect standard for use inside the computer or embedded system enabling faster data transfers to and from peripheral devices. The standard has achieved a degree of stability such that other applications can be implemented using PCIE as basis. A PCIE based interconnect scheme for switching and inter-connection between multiple PCIE enabled systems, each having its own PCIE root complexes controlling a PCIE bus, enabling the scalability of PCIE architecture to be used for data transport between inter-connected PCIE buses of systems forming a cluster using PCIE protocol, through a switch enabled for PCIE interconnect, forming the hub of a star connected network is proposed. These systems forming the cluster can be any computing, control, storage or embedded system. The scalability of the interconnect will allow the cluster to grow the bandwidth between the systems as they become necessary without changing to a different connection architecture.

A communication relay device includes a plurality of LAN ports configured to connect to at least one communication terminal; a first communication unit configured to receive first information transmitted from the at least one communication terminal via the plurality of LAN ports; a processor; and a memory configured to store a program, the program being executed by the processor to cause the processor to: set a LAN (Local Area Network) interface among a plurality of LAN interfaces for each of the plurality of LAN ports; set a MAC address from a plurality of MAC addresses for each of the plurality of LAN interfaces; and control communication so that each of the plurality of LAN interfaces functions as a virtual single switch associated with the MAC address.

A configurable directional 2D router for Networks on Chips (NOCs) is disclosed. The router, which may be bufferless, is designed for implementation in programmable logic in FPGAs, and achieves theoretical lower bounds on FPGA resource consumption for various applications. The router employs an FPGA router switch design that consumes only one 6-LUT or 8-input ALM logic cell per router per bit of router link width. A NOC comprising a plurality of routers may be configured as a directional 2D torus, or in diverse ways, network sizes and topologies, data widths, routing functions, performance-energy tradeoffs, and other options. The router and NOC enable feasible FPGA implementation of large integrated systems on chips, interconnecting hundreds of client cores over high bandwidth links, including compute and accelerator cores, industry standard IP cores, DRAM/HBM/HMC channels, PCI Express channels, and 10G/25G/40G/100G/400G networks.

A configurable directional 2D router for Networks on Chips (NOCs) is disclosed. The router, which may be bufferless, is designed for implementation in programmable logic in FPGAs, and achieves theoretical lower bounds on FPGA resource consumption for various applications. The router employs an FPGA router switch design that consumes only one 6-LUT or 8-input ALM logic cell per router per bit of router link width. A NOC comprising a plurality of routers may be configured as a directional 2D torus, or in diverse ways, network sizes and topologies, data widths, routing functions, performance-energy tradeoffs, and other options. The router and NOC enable feasible FPGA implementation of large integrated systems on chips, interconnecting hundreds of client cores over high bandwidth links, including compute and accelerator cores, industry standard IP cores, DRAM/HBM/HMC channels, PCI Express channels, and 10G/25G/40G/100G/400G networks.

One embodiment of the present invention provides a switching system. The switching system includes a plurality of line cards, each of which includes one or more ports, a processor, one or more switch fabric cards for facilitating switching among the line cards, and a memory storing instructions for facilitating efficient hot-swapping. During operation, the switching system identifies a hot-swapping event of a first switch fabric card based on a data structure indicating the one or more switch fabric cards. The hot-swapping event indicates insertion or removal of the first switch fabric card while the switching system remains in an operational state. The switching system then determines an event type associated with the hot-swapping event and manages the first switch fabric card based on the determined event type.

Embodiments of the present invention relate to the communications field, and provide a multi-chassis cascading apparatus. The apparatus includes a line card chassis LCC, where a fabric interface chip FIC and a switch element SE 1/3 are deployed in each line card chassis LCC; the fabric interface chip FIC is connected to the switch element SE 1/3 that is located in the same line card chassis LCC as the fabric interface chip FIC is; and a switch element SE 2 is deployed in each line card chassis LCC; the switch element SE 1/3 is connected to the switch element SE 2 that is located in the same line card chassis LCC as the switch element SE 1/3 is; and the switch element SE 1/3 is connected to the switch element SE 2 that is located in another line card chassis LCC.

A data center rack includes a housing, at least one wireless access point (AP) mounted within the housing and wirelessly connectable to a network switch external to the housing, and at least one tray including a plurality of mobile device power connections to provide power to a plurality of mobile devices.

A management system is described. The management system includes an interface coupled to a plurality of infrastructure appliances and one or more processors to monitor each of the plurality of infrastructure appliances, detect a malfunction at a first of the infrastructure appliances, and transmit a display message to the first infrastructure appliance including a message to be displayed at one or more activity light indicators at the first infrastructure appliance.

A management system is described. The management system includes an interface coupled to a plurality of infrastructure appliances and one or more processors to monitor each of the plurality of infrastructure appliances, detect a malfunction at a first of the infrastructure appliances, and transmit a display message to the first infrastructure appliance including a message to be displayed at one or more activity light indicators at the first infrastructure appliance.