A programmable switch includes an input arbiter to analyze packet headers of incoming packets and determine which of the incoming packets are part of gradient vectors received from worker computing devices that are performing reinforcement learning. The programmable switch also includes an accelerator coupled to the input arbiter, the accelerator to: receive the incoming packets from the input arbiter; asynchronously aggregate gradient values of the incoming packets, as the gradient values are received, to generate an aggregated data packet associated with a gradient segment of the gradient vectors; and transfer the aggregated data packet to the input arbiter to be transmitted to the worker computing devices, which are to update local weights based on the aggregated data packet.

Embodiments include methods for managing a reordering timer performed by a processor of a wireless device. The processor may receive packets from a communication network and store the packets in a memory buffer of the wireless device. The processor may detect one or more conditions that affect an amount of time required to reorder or reassemble at least some of the packets received from the communication network. The processor may determine a timer adjustment based on the detected one or more conditions. The processor may adjust a timer with the determined timer adjustment. The processor may deliver one or more packets from the memory buffer in response to expiration of the adjusted timer.

Embodiments include methods for managing a reordering timer performed by a processor of a wireless device. The processor may receive packets from a communication network and store the packets in a memory buffer of the wireless device. The processor may detect one or more conditions that affect an amount of time required to reorder or reassemble at least some of the packets received from the communication network. The processor may determine a timer adjustment based on the detected one or more conditions. The processor may adjust a timer with the determined timer adjustment. The processor may deliver one or more packets from the memory buffer in response to expiration of the adjusted timer.

The present invention discloses method for transmitting downlink packet in function-separated core network. It is an object of the embodiments of the present disclosure to provide a method for transmitting a downlink packet for a UE in an idle mode which is capable of reducing a data transmission latency for a user and efficiently using network resources in a mobile communication system in which the control plane and the user plane of a gateway node are separated.

The present invention discloses method for transmitting downlink packet in function-separated core network. It is an object of the embodiments of the present disclosure to provide a method for transmitting a downlink packet for a UE in an idle mode which is capable of reducing a data transmission latency for a user and efficiently using network resources in a mobile communication system in which the control plane and the user plane of a gateway node are separated.

A packet group processor of a network device defines groups of packets among packets that are being processed by the network device, each of at least some of the groups of packets defining a respective group of at least two different packets. Each group includes one or more packets to be transmitted via a respective same network interface. A transmit processor makes a single transmit decision that a particular group of at least two packets is to be transmitted via a corresponding network interface, and in response to the single transmit decision, transfers the particular group of at least two packets to the corresponding network interface for transmission.

A packet group processor of a network device defines groups of packets among packets that are being processed by the network device, each of at least some of the groups of packets defining a respective group of at least two different packets. Each group includes one or more packets to be transmitted via a respective same network interface. A transmit processor makes a single transmit decision that a particular group of at least two packets is to be transmitted via a corresponding network interface, and in response to the single transmit decision, transfers the particular group of at least two packets to the corresponding network interface for transmission.

Orders received by an electronic trading system are processed in batches based on the instrument to which an order relates. An incoming order is assigned to a queue of a queue set that makes up the batch according to a random process. Where orders are received from related trading parties, they are assigned to the same queue set according to their time of receipt. The batch has a random duration within defined minimum and maximum durations and at the end of the batch, the orders held in the queues are transferred to a matching thread of the trading system sequentially with one order being removed from each queue and a number of passes of the queues completed until orders have been removed.

Packets received by a network switch device from upstream network devices, coupled to respective ones of a plurality of ports of the network switch device, are temporarily stored in an internal memory of the network switch device. In response to detecting congestion in the internal memory of the network switch device, a flow control engine triggers, during respective timeslots of a timing schedule and while the flow control engine continues to monitor congestion in the internal memory of the network switch device, transmission of respective flow control messages via different subsets of ports, among the plurality of ports, to control flow of packets from different subsets of upstream network device, among the plurality of upstream network devices, to the network switch device so that flow control is distributed over time among upstream network devices of the plurality of upstream network devices.

A network interface device has data path circuitry configured to cause data to be moved into and/or out of the network interface device. The data path circuitry comprises: first circuitry for providing one or more data processing operations; and interface circuitry supporting channels. The channels comprises command channels receiving command information from a plurality of data path circuitry user instances, event channels providing respective command completion information to the plurality of data path user instances; and data channels providing the associated data.