A processor device has an executable implementation of a cryptographic algorithm implemented being white-box-masked by a function f. The implementation comprises an implemented computation step S by which input values x are mapped to output values s=S[x], and which is masked to a white-box-masked computation step T by means of an invertible function f. As a mapping f there is provided a combination (f=(c1, c2, . . . )*A) of an affine mapping A having an entry width BA and a number of one or several invertible mappings c1, c2, . . . having an entry width Bc1, Bc2, . . . respectively, wherein BA=Bc1+Bc2+ . . . . Output values w are generated altogether by the mapping f. Multiplicities of sets Mxi, i=1, 2, . . . =Mx11, Mx12, . . . Mx21, Mx22, . . . are formed from the output values a of the affine mapping A.

Disclosed are a system and method for generating a symmetrically balanced output to accomplish a plurality of predefined properties. The method comprises a step of receiving a plurality of registers with B bits, an expression length, and a plurality of operators through a receiving module. The method then includes a step of generating a random expression population through a random expression population generation module. Further, the method includes the step of computing a fitness value of the random expression population through a fitness function module. The method then includes the step of providing registers with B bits if a plurality of output bits are having an equal number of 1s and 0s through a conditional module. The conditional module performs mutation in the operators if the output bits are not having an equal number of 1s and 0s.

Various techniques provide systems and methods for facilitating iterative key generation and data encryption and decryption. In one example, a method includes encrypting, by an encryption logic circuit, a current data portion of plaintext data using a current encryption key to provide an encrypted current data portion. The method further includes generating, by the encryption logic circuit, a next encryption key for encryption of a next data portion of the plaintext data based on the current encryption key. Related methods and devices are also provided.

The present disclosure presents methods, apparatuses, and systems to bolster communication security, and more particularly to utilize a constant time cryptographic co-processor engine for such communication security. For example, the disclosure includes a method for secure communication, comprising receiving encrypted data at a receiving device; obtaining a randomization for at least one bit of the encrypted data; modifying an execution of a cryptographic algorithm on the at least one bit to obtain a randomized cryptographic algorithm based on the randomization; and executing the randomized cryptographic algorithm on the at least one bit of encrypted data to recover original data associated with the encrypted data.

In a general aspect, a test method can include acquiring a plurality of value sets, each including values of a physical quantity or of logic signals, linked to the activity of a circuit to be tested when executing distinct cryptographic operations applied to a same secret data, for each value set, counting occurrence numbers of the values of the set, for each operation and each of the possible values of a part of the secret data, computing a partial result of operation, computing sums of occurrence numbers, each sum being obtained by adding the occurrence numbers corresponding to the operations which when applied to a same possible value of the part of the secret data, provide a partial operation result having a same value, and analyzing the sums of occurrence numbers to determine the part of the secret data.

The application relates to a method for computing a probabilistic encryption scheme for encrypting a data item in an electronic device including: computing a plurality of random bit strings in a computation cluster; sending the computed plurality of random strings to the electronic device; generating a random string (r.sub.E) for using in the encryption scheme in the electronic device using a subset of the plurality of the random strings computed in the computation cluster and encrypting the data item using the random string computed in the electronic device. The present application also relates to a corresponding system and corresponding computer program product including one or more computer readable media having computer executable instructions for performing the steps of the method.

Apparatus and method for resisting side-channel attacks on cryptographic engines are described herein. An apparatus embodiment includes a cryptographic block coupled to a non-linear low-dropout voltage regulator (NL-LDO). The NL-LDO includes a scalable power train to provide a variable load current to the cryptographic block, randomization circuitry to generate randomized values for setting a plurality of parameters, and a controller to adjust the variable load current provided to the cryptographic block based on the parameters and the current voltage of the cryptographic block. The controller to cause a decrease in the variable load current when the current voltage is above a high voltage threshold, an increase in the variable load current when the current voltage is below a low voltage threshold; and a maximization of the variable load current when the current voltage is below an undervoltage threshold. The cryptographic block may be implemented with arithmetic transformations.

An apparatus configured to: receive a digital input signal; receive a processing-direction-signal that can have a forward-value or a backward-value; and provide a digital output signal. The apparatus comprising a processor configured to apply an involutional cryptographic function to the digital input signal by: for a first operation: apply a first step of the involutional cryptographic function to the digital input signal in order to implement a forward calculation to move to the next step in the sequence; and perform a plurality of further operations until the forward calculation of a last step is performed. Each further operation comprises: if the processing-direction-signal has a forward-value: then perform the forward calculation for the current step; or if the processing-direction-signal has a backward-value: then perform a backward calculation for the current step.

A method for executing a function, secured by temporal desynchronization, includes when a first legitimate instruction is loaded, noting the opcode of this first legitimate instruction, then constructing a dummy instruction on the basis of this noted opcode, the dummy instruction thus constructed being identical to the first legitimate instruction except that its operands are different, then incorporating the dummy instruction thus constructed into a sequence of dummy instructions used to delay the time at which a second legitimate instruction is executed.

The invention is a process with operations or steps by which separate systems can communicate information and data through encrypted transmissions of data which may include strings, numbers, or other characters. This ensures that the messages are secure from eavesdropping and imitation by third parties. Security is further enhanced by using a method of reduced character sets to transmit data between systems by means of meta bits that allow single encrypted data items to represent multiple possible meanings. The receiving system uses these details to check the integrity of the data and sending system before decrypting the message. A similar method is used by the receiving system to encrypt its output before returning it to the original system. This results in a bi-directional encrypted messaging system that is impervious to outside attempts at decryption.