H04L2209/12

Method and apparatus for encrypting and decrypting data on an integrated circuit
11429751 · 2022-08-30 · ·

The disclosure is generally directed to a method and apparatus for encrypting and decrypting data on an integrated circuit. In various implementations, the apparatus includes an on-chip high performance bus bridge that transparently encrypts and decrypts data between the embedded microprocessor(s) and off-chip system memory. In some implementations, the apparatus is optimized to the transactions generated by the processor's cache controller (e.g., optimized for cache line size) and optimized to the bus protocol being used. This provides code protection with minimal effect on system performance latency and throughput. The implementation of multiple cryptographic engines allows for encryption of a complete cache line while incurring only a single latency for the first cipher rounds to be completed.

CIRCUIT PROTECTION SYSTEM AND METHOD

The invention proposes a method of protection of a Boolean circuit associated with a structural description of the circuit comprising elementary Boolean variables, each represented by one bit, the method comprising the steps consisting in: selecting a set of k elementary Boolean variables of the circuit as a function of predefined selection criteria, constructing a variable x represented by k bits by concatenation of the k selected variables in accordance with a chosen order, determining a binary code C comprising a set of code words and belonging to a given vector space and the supplementary code D of said binary code C as a function of a condition bearing on the dual distance of said supplementary code D, said binary code C having a length n and a size 2.sup.k, where k designates the number of bits representing said variable x; substituting the variable x in the structural description of the Boolean circuit with a protected variable z represented by n bits so that: any operation of writing on the variable x in the circuit is substituted with an operation of writing on the variable z, the variable z being generated by adding the variable x encoded by said code C to a random bit vector y encoded by the supplementary code D, and any operation of reading the variable x in the circuit is substituted with an operation of reading the value of the protected variable z and an operation of decoding said read value of the protected variable z using a decoding matrix J of size (n×k) determined from the binary code C and the supplementary code D of the binary code C.

PHYSICAL UNCLONABLE FUNCTION
20170230188 · 2017-08-10 · ·

Apparatus, electronic device, system and method comprising a first element (102) configured to receive a first signal and convert the first signal to a second signal, a second element (104) configured to relay the second signal to a third element (106, 108), the third element (106, 108) being configured to convert the second signal to a third signal and to send the third signal; wherein the first element (102) is configured to convert the first signal to the second signal in such a way that the conversion is dependent on the physio-chemical structure of at least part of the first element (102). In some embodiments the first element comprises a photoacoustic sensor comprising at least one graphene layer, the second element comprises a mechanical wave transmission line, and the third element comprises carbon nanotube antennas.

SEMICONDUCTOR MEMORY DEVICES AND METHODS OF MANUFACTURING THEREOF

A memory system includes a memory array comprising a plurality of memory cells. Each of the memory cells includes a transistor coupled to a first capacitor and a second capacitor in series, respectively. The memory system includes an authentication circuit operatively coupled to the memory array. The authentication circuit is configured to generate a Physically Unclonable Function (PUF) signature based on respective logic states of the plurality of memory cells, and wherein the logic state of each of the plurality of memory cells is determined based on a preceding breakdown of either the corresponding first capacitor or second capacitor.

Key management for on-the-fly hardware decryption within integrated circuits

Methods and systems are disclosed for key management for on-the-fly hardware decryption within an integrated circuit. Encrypted information is received from an external memory and stored in an input buffer within the integrated circuit. The encrypted information includes one or more encrypted key blobs. The encrypted key blobs include one or more secret keys for encrypted code associated with one or more encrypted software images stored within the external memory. A key-encryption key (KEK) code for the encrypted key blobs is received from an internal data storage medium within the integrated circuit, and the KEK code is used to generate one or more key-encryption keys (KEKs). A decryption system then decrypts the encrypted key blobs using the KEKs to obtain the secret keys, and the decryption system decrypts the encrypted code using the secret keys. The resulting decrypted software code is then available for further processing.

Physical Unclonable Function Variable Read Sensor

Magnetic PUFs (Physical Unclonable Function) may utilizes a single 3-axis Hall-effect sensor for enrollment. When a PUF is manufactured, a Hall-effect sensor is used to model the PUF disk and store that data where it may be accessed. This process is called “enrollment.” This invention improves upon the PUF implementation by introducing controlled variability into the enrollment, the reading of the PUF data from the Hall-effect sensors (the number and position of read sensors), the sampling method of the read sensor(s), and the processing of the PUF data.

Cryptography method and circuit, corresponding device

A cryptographic method includes providing memory locations for storing encrypted data. The memory locations have respective addresses and are accessible via a communication bus. The method includes receiving over the communication bus access requests to the memory locations, wherein the access requests include burst requests for access to respective sets of the memory locations starting from respective start addresses, and calculating as a function of the start addresses encryption/decryption cryptographic masks based on cryptographic keys. Plain text data is received for encryption and the method includes applying the cryptographic masks to the plain text data to obtain therefrom encrypted data, and including the encrypted data into output data for transmission over the communication bus.

Method of operation for a configurable number theoretic transform (NTT) butterfly circuit for homomorphic encryption

Fully homomorphic encryption integrated circuit (IC) chips, systems and associated methods are disclosed. In one embodiment, a method of operation for a number theoretic transform (NTT) butterfly circuit is disclosed. The (NTT) butterfly circuit includes a high input word path cross-coupled with a low word path. The high input word path includes a first adder/subtractor, and a first multiplier. The low input word path includes a second adder/subtractor, and a second multiplier. The method includes selectively bypassing the second adder/subtractor and the second multiplier, and reconfiguring the low and high input word paths into different logic processing units in response to different mode control signals.

Secure computation system, secure computation apparatus, secure computation method, and recording medium

P.sub.i and P.sub.+ have stored a.sub.+∈{a.sub.0, a.sub.1, a.sub.2} and b.sub.+∈{b.sub.0, b.sub.1, b.sub.2} therein, and P.sub.i and P.sub.− have stored a.sub.−∈A.sub.− and b.sub.−∈B.sub.− therein. Here, P.sub.+−P.sub.(i+1)mod 3, P.sub.−=P.sub.(i−1)mod 3, and a and b are arbitrary values and satisfy a=a.sub.0+a.sub.1+a.sub.2 and b=b.sub.0+b.sub.1+b.sub.2, where A.sub.− is a complement of a.sub.+ in {a.sub.0, a.sub.1, a.sub.2} and B.sub.− is a complement of b.sub.+ in {b.sub.0, b.sub.1, b.sub.2}. P.sub.i and P.sub.+ share r.sub.+, P.sub.i and P.sub.− share r.sub.−, and P.sub.i calculates c.sub.+=(a.sub.++a.sub.−)(b.sub.++b.sub.−)−a.sub.−b.sub.−+r.sub.+−r.sub.−. P.sub.i sends c.sub.+ to P.sub.+.

Data encryption in medical devices with limited computational capability

A medical device with limited computational capability includes medical hardware, a first register to store a static, substantially unique identifier of the medical device, a second register to store a static encryption key, an interface to receive and transmit data over a short-range communication link, and processing hardware. The processing hardware is configured to apply the static encryption key to the identifier of the medical device to generate an encrypted identifier, transmit the encrypted identifier of to another device via the interface, receive an encrypted identifier of the other device, decrypt the encrypted identifier of the other device using the static encryption key to determine an identifier of the other device, generate a dynamic encryption key using the identifier of the medical device and the identifier of the other device, and apply the dynamic encryption key to medical data transmitted between the medical device and the other device.