A message authenticator generating apparatus, taking as input a key K and a message M, generates an i-times-e-bit value E, and divides the value E at every e bit to generate values M[1], . . . , M[i]. During this, the message authenticator generating apparatus generates the value E such that a value M[1] and a value M[i] out of the values M[1], . . . , M[i] include at least one of bits of the key K. The message authenticator generating apparatus, where a value S[0] is an arbitrary value, for each integer j of j=1, . . . , i in an ascending order, calculates a value R[j] by a function g[j] taking as input a value S[j1] and a value M[j], and substitutes the calculated value R[j] by a substitution function P[j] to calculate a value S[j]. The message authenticator generating apparatus generates an authenticator T for the message M with using a value S[i].

Method and apparatus are disclosed for remote keyless entry authentication. An example remote keyless entry system includes a key fob and a vehicle. The key fob generates a secured message with a plaintext space and a ciphertext space. The vehicle (i) determines whether the key fob may be authorized based on first information in the plaintext space, (ii) decrypts an encrypted value in the ciphertext space based on a predicted full counter value, and (iii) determines whether the key fob is authorized based on second information in the encrypted value.

A secure memory, key expansion logic, and decryption logic are provided for a microprocessor that executes encrypted instructions. The secure memory stores a plurality of decryption key primitives. The key expansion logic selects two or more decryption key primitives from the secure memory and then derives a decryption key from them. The decryption logic uses the decryption key to decrypt an encrypted instruction fetched from the instruction cache. The decryption key primitives are selected on the basis of an encrypted instruction address, one of them is rotated by an amount also determined by the encrypted instruction address, and then they are additively or subtractively accumulated, also on the basis of the encrypted instruction address.

A computerized process is described for improving a computer's digital signing capabilities that results in digital signatures that are substantially more secure with enhanced proof of data integrity, signatory authentication, and signatory non-repudiation without modification to underlying signature algorithms. The process utilizes computing resources, plaintext to be signed, and eight asymmetric cryptography digital signature algorithms each utilizing a specified hash algorithm and different private key from a public-private key pair. A novel mechanism is described that copies bit values from common bit positions of plaintext bytes into eight partitions. Each partition of bytes is independently signed using a signature algorithm and the resulting partitions of signed bytes are combined to form a digital signature. As the digital signature verification requires eight signature algorithms each utilizing a specified hash algorithm and a public key from the public-private key pair used for signing, such digital signature is significantly improved over signing with a single signature algorithm utilizing a hash algorithm and key.

An instruction to be used to produce a message digest for a message is executed. In execution, a padding state control of the instruction is checked to determine whether padding has been performed for the message. If the checking indicates padding has been performed, a first action is performed; and if the checking indicates padding has not been performed, a second action, different from the first action, is performed.

Systems, methods, and computer-readable media are disclosed for performing message padding of input messages in a manner that preserves the integrity of the input data regardless of whether the input message is in a bit-oriented format or a bit-reversed format. Each byte of a partial input message block of an input message may be converted from a bit-reversed format to a bit-oriented format prior to performing message padding in order to ensure that input data bits are not lost during the message padding. Subsequent to the message padding that generates one or more padded message blocks, the padded message block(s) may be converted from a bit-oriented format to a bit-reversed format to enable further processing of the input message to be performed to obtain a message digest.

Systems, methods, and computer-readable media are disclosed for processing and message padding an input message as well as processing an extended output message (EOM) in a manner that ensures that the input message and the padded message are processed only a single time, thus avoiding generation of an incorrect message digest. In addition, in those scenarios in which multiple padded message blocks are generated, the disclosed systems, methods, and computer-readable media ensure that all of the padded message blocks are processed.

A transmission circuit includes: a transmission-side generation circuit configured to extract data at a predetermined byte position from user data to be transmitted, and to generate a transmission random pattern having a predetermined bit length by performing predetermined calculation processing using a value of the extracted data; a calculation circuit configured to generate transmission byte scrambled data by performing calculation on each byte of the user data and the generated transmission random pattern; a transmission-data coupling circuit configured to generate transmission scrambled data by coupling the generated transmission byte scrambled data and the data extracted by the transmission-side generation circuit; and a data-generation circuit configured to generate, from the transmission scrambled data, transmission data to be transmitted from the transmission circuit.

One embodiment provides an apparatus. The apparatus includes a single instruction multiple data (SIMD) hash module configured to apportion at least a first portion of a message of length L to a number (S) of segments, the message including a plurality of sequences of data elements, each sequence including S data elements, a respective data element in each sequence apportioned to a respective segment, each segment including a number N of blocks of data elements and to hash the S segments in parallel, resulting in S segment digests, the S hash digests based, at least in part, on an initial value and to store the S hash digests; a padding module configured to pad a remainder, the remainder corresponding to a second portion of the message, the second portion related to the length L of the message, the number of segments and a block size; and a non-SIMD hash module configured to hash the padded remainder, resulting in an additional hash digest and to store the additional hash digest.

A microprocessor is provided in which an encrypted program can replace the decryption keys that are used to decrypt sections of the encrypted program. The microprocessor may be decrypting and executing a first section of the encrypted program when it encounters, decrypts, and executes an encrypted store-key instruction to store a new set of decryption keys. After executing the store-key instruction, the microprocessor decrypts and executes a subsequent section of the encrypted program using the new set of decryption keys. On-the-fly key switching may occur numerous times with successive encrypted store-key instructions and successive sets of encrypted instructions.