H04L2209/34

Format-preserving cryptographic systems
11488134 · 2022-11-01 · ·

Format-preserving encryption and decryption processes are provided. The encryption and decryption processes may use a block cipher. A string that is to be encrypted or decrypted may be converted to a unique binary value. The block cipher may operate on the binary value. If the output of the block cipher that is produced is not representative of a string that is in the same format as the original string, the block cipher may be applied again. The block cipher may be repeatedly applied in this way during format-preserving encryption operations and during format-preserving decryption operations until a format-compliant output is produced. Selective access may be provided to portions of a string that have been encrypted using format-preserving encryption.

Adjusting Error Encoding Parameters for Writing Encoded Data Slices

A method includes writing sets of encoded data slices to storage units of a storage network in accordance with error encoding parameters, where for a set of encoded data slices, the error encoding parameters include an error coding number and a decode threshold number, the error coding number indicates a number of encoded data slices that results when a data segment is encoded using an error encoding function and the decode threshold number indicates a minimum number needed to recover the data segment. The method further includes monitoring processing of the writing the sets of encoded data slices to produce write processing performance information. When the write processing performance information compares unfavorably to a desired write performance range, the method further includes adjusting at least one of the error coding number and the decode threshold number to produce adjusted error encoding parameters for writing subsequent encoded data slices.

Key encapsulation protocols

Some embodiments are directed to a cryptographic device (20). A reliable bit function may be applied to a raw shared key (k*) to obtain reliable indices, indicating coefficients of a raw shared key, and reliable bits derived from the indicated coefficients. Reconciliation data (h) may be generated for the indicated coefficients of the raw shared key. A code word may be encapsulated using the reliable bits by applying an encapsulation function, obtaining encapsulated data (c) which may be transferred.

METHOD OF CONSTRUCTING A SEMI-PUBLIC KEY SYSTEM IN QAP-BASED HOMOMORPHIC ENCRYPTION
20230128727 · 2023-04-27 ·

The method of constructing QAP-based Homomorphic Encryption (HE) in the semi-public setting is introduced, which comprises: encryption, computation, and decryption. The data receiver produces a semi-public key Key.sub.s-pub.The data provider can encode his k-qubit plaintext |xcustom-character to a k-qubit ciphertext |ψ.sub.encustom-character=Q.sub.P|xcustom-character via a k-qubit invertible operator Q.sub.P randomly generated by Key.sub.s-pub. From the provider, the message En(ζ.sub.p) of Q.sub.P encoded by a cryptosystem G.sub.crypt in Key.sub.s-pub is transmitted to the receiver through a small-resource communication channel and the ciphertext |ψ.sub.encustom-character is conveyed to the cloud. The receiver creates the instruction of encoded computation U.sub.en=Pcustom-characterMQ.sub.P and transports to the cloud, where M is the required k-qubit arithmetic operation, P a k-qubit permutation, and custom-character a k-qubit operator to mingle with M. According the instruction, the cloud performs the encrypted evaluation U.sub.en|ψ.sub.encustom-character and transfer to the receiver. The decryption Key.sub.privU.sub.en|ψ.sub.encustom-character is conducted by the receiver via the private key Key.sub.priv=<

MEMORY SYSTEMS AND DEVICES INCLUDING EXAMPLES OF ACCESSING MEMORY AND GENERATING ACCESS CODES USING AN AUTHENTICATED STREAM CIPHER
20230126741 · 2023-04-27 · ·

Examples of systems and method described herein provide for accessing memory devices and, concurrently, generating access codes using an authenticated stream cipher at a memory controller. For example, a memory controller may use a memory access request to, concurrently, perform translation logic and/or error correction on data associated with the memory access request; while also utilizing the memory address as an initialization vector for an authenticated stream cipher to generate an access code. The error correction may be performed subsequent to address translation for a write operation (or prior to address translation for a read operation) to improve processing speed of memory access requests at a memory controller; while the memory controller also generates the encrypted access code.

METHOD OF OPERATING STORAGE DEVICE AND METHOD OF OPERATING STORAGE SYSTEM USING THE SAME
20230128638 · 2023-04-27 ·

In a method of operating a storage device including a plurality of storage regions, a first request is received. The first request is for a cryptographic erasure with respect to a first storage region. During a first time interval, a first encryption key corresponding to the first storage region is changed based on the first request. A second request is received. In response to receiving the second request within the first time interval, a region access signal is outputted. In response to determining, based on the region access signal, that the second request is associated with the first storage region, an execution of the second request is held. In response to determining, based on the region access signal, that the second request is associated with a second storage region among the plurality of storage regions, the second request is executed.

Cryptographic Computer Machines with Novel Switching Devices
20230125560 · 2023-04-27 ·

Operational n-state digital circuits and n-state switching operations with n and integer greater than 2 execute Finite Lab-transformed (FLT) n-state switching functions to process n-state signals provided on at least 2 inputs to generate an n-state signal on an output. The FLT is an enhancement of a computer architecture. Cryptographic apparatus and methods apply circuits that are characterized by FLT-ed addition and/or multiplication over finite field GF(n) or by addition and/or multiplication modulo-n that are modified in accordance with reversible n-state inverters, and are no longer known operations. Cryptographic methods processed on FLT modified machine instructions include encryption/decryption, public key generation, and digital signature methods including Post-Quantum methods. They include modification of isogeny based, NTRU based and McEliece based cryptographic machines.

Method for communication between first and second nodes in a network

Some protocols for the transmission of data on a communication network, such as the LoRaWAN protocol, use frames comprising payloads intended to transport useful data, the size of which may vary from one frame to another. A communication method is proposed in order to transmit data on this type of network. This method is based on a division of a payload packet into a set of blocks and then an insertion of the blocks thus formed into at least one segment. Each segment comprises a number of blocks suited to a payload size at the time of creation of the segment. The segments are next supplemented with verification information enabling an addressee of the data packet to determine whether it has received all the blocks. In the event of non-reception of all the blocks, the sender of the blocks retransmits at least the blocks not received.

Quantum neural network
11601265 · 2023-03-07 · ·

A quantum neural network architecture. In one aspect, a quantum neural network trained to perform a machine learning task includes: an input quantum neural network layer comprising (i) multiple qubits prepared in an initial quantum state encoding a machine learning task data input, and (ii) a target qubit; a sequence of intermediate quantum neural network layers, each intermediate quantum neural network layer comprising multiple quantum logic gates that operate on the multiple qubits and target qubit; and an output quantum neural network layer comprising a measurement quantum gate that operates on the tar get qubit and provides as output data representing a solution to the machine learning task.

Arithmetic enhancement of C-like smart contracts for verifiable computation

A system converts high level source code into an arithmetic circuit that represents the functionality expressed in the source code, such as a smart contract as used in relation to a blockchain platform. The system processes a portion of high level source code to generate an arithmetic circuit. The arithmetic circuit comprises one or more arithmetic gates arranged to represent at least some of the functionality expressed in the source code.