A system may comprise a first device and a second device associated with a Clos architecture. The first device may include a first crossbar that comprises a first component, a second component, and a third component. The second device may include a second crossbar that comprises a fourth component, a fifth component, and a sixth component. The first component may connect to the second component and the fifth component. The second component may connect to the first component, the third component, the fourth component, and the sixth component. The third component may connect to the second component and the fifth component. The fourth component may connect to the second component and the fifth component. The fifth component may connect to the first component, the third component, the fourth component, and the sixth component. The sixth component may connect to the second component and the fifth component.

A hybrid processor system for use on board a telecommunications multi-beam satellite is provided that is controllable by a network control centre via one or more control channels. The system links to ground terminals by: providing uplink and downlink traffic channels on several satellite beams; routing atomic switched information blocks from the uplink traffic channels to the downlink traffic channels; and exchanging signaling data with the ground terminals on one or more uplink signaling channels and one or more downlink signaling channels. The atomic switched information blocks have the same given time duration and the same given baseband bandwidth. The hybrid processor system includes a burst switching processor and an on-board processor controller which is configured to store service information items indicative of: the given time duration and the given baseband bandwidth of the atomic switched information blocks; the respective uplink bandwidth, the respective uplink frequencies, a respective time length of the respective uplink time slots, and respective structure features of the respective uplink time frames and superframes of each uplink channel; the respective downlink bandwidth, the respective downlink frequencies, a respective time length of the respective downlink time slots, and respective structure features of the respective downlink time frames and superframes of each downlink channel; and quality of service and priority rules for serving the ground terminals. The on-board processor controller is further configured to extract, from incoming signaling data capacity requests sent by the ground terminals by demodulating and decoding the incoming signaling data.

Sparse representation of information performs powerful feature extraction on high-dimensional data and is of interest for applications in signal processing, machine vision, object recognition, and neurobiology. Sparse coding is a mechanism by which biological neural systems can efficiently process complex sensory data while consuming very little power. Sparse coding algorithms in a bio-inspired approach can be implemented in a crossbar array of memristors (resistive memory devices). This network enables efficient implementation of pattern matching and lateral neuron inhibition, allowing input data to be sparsely encoded using neuron activities and stored dictionary elements. The reconstructed input can be obtained by performing a backward pass through the same crossbar matrix using the neuron activity vector as input. Different dictionary sets can be trained and stored in the same system, depending on the nature of the input signals. Using the sparse coding algorithm, natural image processing is performed based on a learned dictionary.

Sparse representation of information performs powerful feature extraction on high-dimensional data and is of interest for applications in signal processing, machine vision, object recognition, and neurobiology. Sparse coding is a mechanism by which biological neural systems can efficiently process complex sensory data while consuming very little power. Sparse coding algorithms in a bio-inspired approach can be implemented in a crossbar array of memristors (resistive memory devices). This network enables efficient implementation of pattern matching and lateral neuron inhibition, allowing input data to be sparsely encoded using neuron activities and stored dictionary elements. The reconstructed input can be obtained by performing a backward pass through the same crossbar matrix using the neuron activity vector as input. Different dictionary sets can be trained and stored in the same system, depending on the nature of the input signals. Using the sparse coding algorithm, natural image processing is performed based on a learned dictionary.

A non-blocking crossbar switch architecture circumvents the problem present in prior art crossbar switches where input signals may oversubscribe the available inter-die bandwidth. The new non-blocking crossbar switch architecture is split across a plurality of semiconductor dice, including a plurality of interleaved crossbar switch segments. Only one crossbar switch segment is implemented on each semiconductor die. A plurality of input ports and output ports are coupled to the crossbar switch. The crossbar switch is non-blocking, i.e., any one output port not currently receiving data may receive data from any one input port.

A computing system includes a streaming engine and a graph core. The streaming engine includes an array of compute units (CUs), an array of crossbar switches, and a configurable interconnect circuit. The CUs perform logical operations on operands. The crossbar switches forward outputs of one or more CUs to inputs of one or more neighboring CUs. The configurable interconnect circuit forwards an output of at least one of the CUs to an input of at least one of the crossbar switches. The graph core programs the streaming processor to perform a security computation by selectively configuring the CUs to perform a plurality of respective logical operations in a programmable order to define a flow of logical operations to be performed by the CUs that effects the security computation, and configuring the crossbar switches and the interconnect circuit to perform the logical operations by traversing the CUs according to the flow.