The present invention relates in general to communication systems, and more specifically towards methods, systems, and devices that help improve transmission rates and spectral efficiency of intensity modulated (IM) or power modulated channels utilizing multi-level pulse amplitude modulation PAM-M. In an embodiment, the present invention used an iterative algorithm to open the eyes of an eye diagram in a relatively short number of steps. The algorithm, which may not require previous characterization of the channel, utilizes pseudo-random sequences, such as PSBS15 or PRQS10, and adaptive non-linear equalizers to optimize the pre-distortion taps.

A serial transmitter that outputs one symbol every unit interval (UI) from a data source is presented. The serial transmitter includes a serial output port that outputs one symbol every unit interval (UI) from a data source. The serial transmitter also includes a plurality of driver segments that jointly drive the serial output port. Each driver segment is configured to use one of N phases of a sampling clock to serialize and transmit data from the data source. Different sets of the driver segments are configured to use different phases of the sampling clock for serializing and transmitting data, the sampling clock being a half-rate clock having a period of two UI.

The present invention is directed to communication systems. According to embodiments of the present invention, a communication system includes at least two communication lanes and a skew management module. The skew management module generates a control current based on output test patterns of the two communication lanes. The control current is integrated and compared to a reference voltage by a comparator, which generates an analog offset signal. A PLL of one of the communication lanes generates a corrected clock signal that is adjusted using the analog offset signal to remove or adjust the skew between the communication lanes. The corrected clock signal is used for output data. There are other embodiments as well.

Digital receiver systems and clock recovery techniques for use in digital receiver systems are provided to implement asynchronous baud-rate clock recovery systems for high data rate serial receivers multilevel line modulation. A two-stage postcursor ISI equalization system is provided to efficiently emulate a 4-level DFE (decision feedback equalization) system, for example, while converting a 4-level equalized signal to s 2-level equalized signal. For example, a two stage postcursor ISI equalization system includes a DFE stage which operates on a most significant component of a given 4-level data symbol, followed by a DFFE (decision-feedforward equalizer) stage which operates on a least significant component of the given 4-level data symbol. In parallel with the DFFE stage, an estimate of the least significant component is subtracted from the equalized 4-level data symbol to convert the 4-level data symbol to a 2-level symbol.

Digital receiver systems and clock recovery techniques for use in digital receiver systems are provided to implement asynchronous baud-rate clock recovery systems for high data rate serial receivers multilevel line modulation. A two-stage postcursor ISI equalization system is provided to efficiently emulate a 4-level DFE (decision feedback equalization) system, for example, while converting a 4-level equalized signal to s 2-level equalized signal. For example, a two stage postcursor ISI equalization system includes a DFE stage which operates on a most significant component of a given 4-level data symbol, followed by a DFFE (decision-feedforward equalizer) stage which operates on a least significant component of the given 4-level data symbol. In parallel with the DFFE stage, an estimate of the least significant component is subtracted from the equalized 4-level data symbol to convert the 4-level data symbol to a 2-level symbol.

Digital receiver systems and clock recovery techniques for use in digital receiver systems are provided to implement asynchronous baud-rate clock recovery systems for high data rate serial receivers multilevel line modulation. A two-stage postcursor ISI equalization system is provided to efficiently emulate a 4-level DFE (decision feedback equalization) system, for example, while converting a 4-level equalized signal to s 2-level equalized signal. For example, a two stage postcursor ISI equalization system includes a DFE stage which operates on a most significant component of a given 4-level data symbol, followed by a DFFE (decision-feedforward equalizer) stage which operates on a least significant component of the given 4-level data symbol. In parallel with the DFFE stage, an estimate of the least significant component is subtracted from the equalized 4-level data symbol to convert the 4-level data symbol to a 2-level symbol.

The present invention is directed to communication systems. According to embodiments of the present invention, a communication system includes at least two communication lanes and a skew management module. The skew management module generates a control current based on output test patterns of the two communication lanes. The control current is integrated and compared to a reference voltage by a comparator, which generates an analog offset signal. A PLL of one of the communication lanes generates a corrected clock signal that is adjusted using the analog offset signal to remove or adjust the skew between the communication lanes. The corrected clock signal is used for output data. There are other embodiments as well.

Digital receiver systems and clock recovery techniques for use in digital receiver systems are provided to implement asynchronous baud-rate clock recovery systems for high data rate serial receivers multilevel line modulation. A two-stage postcursor ISI equalization system is provided to efficiently emulate a 4-level DFE (decision feedback equalization) system, for example, while converting a 4-level equalized signal to s 2-level equalized signal. For example, a two stage postcursor ISI equalization system includes a DFE stage which operates on a most significant component of a given 4-level data symbol, followed by a DFFE (decision-feedforward equalizer) stage which operates on a least significant component of the given 4-level data symbol. In parallel with the DFFE stage, an estimate of the least significant component is subtracted from the equalized 4-level data symbol to convert the 4-level data symbol to a 2-level symbol.

Digital receiver systems and clock recovery techniques for use in digital receiver systems are provided to implement asynchronous baud-rate clock recovery systems for high data rate serial receivers multilevel line modulation. A two-stage postcursor ISI equalization system is provided to efficiently emulate a 4-level DFE (decision feedback equalization) system, for example, while converting a 4-level equalized signal to s 2-level equalized signal. For example, a two stage postcursor ISI equalization system includes a DFE stage which operates on a most significant component of a given 4-level data symbol, followed by a DFFE (decision-feedforward equalizer) stage which operates on a least significant component of the given 4-level data symbol. In parallel with the DFFE stage, an estimate of the least significant component is subtracted from the equalized 4-level data symbol to convert the 4-level data symbol to a 2-level symbol.

Digital receiver systems and clock recovery techniques for use in digital receiver systems are provided to implement asynchronous baud-rate clock recovery systems for high data rate serial receivers multilevel line modulation. A two-stage postcursor ISI equalization system is provided to efficiently emulate a 4-level DFE (decision feedback equalization) system, for example, while converting a 4-level equalized signal to a 2-level equalized signal. For example, a two stage postcursor ISI equalization system includes a DFE stage which operates on a most significant component of a given 4-level data symbol, followed by a DFFE (decision-feedforward equalizer) stage which operates on a least significant component of the given 4-level data symbol. In parallel with the DFFE stage, an estimate of the least significant component is subtracted from the equalized 4-level data symbol to convert the 4-level data symbol to a 2-level symbol.