H04W36/10

Method for establishing tunnel between local gateways, and gateway

A method for establishing a tunnel between local gateways, and a gateway are disclosed. The method includes: determining, by an RGW, that UE is handed over from an S-LGW to a T-LGW, where before the UE is handed over, a packet of a local service of the UE is forwarded by the S-LGW between the UE and an application server of the local service, and the local service includes a same service that is deployed on the S-LGW and that is accessed by the UE before and after the UE is handed over; sending, by the RGW to the S-LGW and the T-LGW respectively, a first request message and a second request message to request to establish a tunnel, where the tunnel is used to transmit the packet of the local service between the S-LGW and the T-LGW; and establishing the tunnel between the S-LGW and the T-LGW.

Method for establishing tunnel between local gateways, and gateway

A method for establishing a tunnel between local gateways, and a gateway are disclosed. The method includes: determining, by an RGW, that UE is handed over from an S-LGW to a T-LGW, where before the UE is handed over, a packet of a local service of the UE is forwarded by the S-LGW between the UE and an application server of the local service, and the local service includes a same service that is deployed on the S-LGW and that is accessed by the UE before and after the UE is handed over; sending, by the RGW to the S-LGW and the T-LGW respectively, a first request message and a second request message to request to establish a tunnel, where the tunnel is used to transmit the packet of the local service between the S-LGW and the T-LGW; and establishing the tunnel between the S-LGW and the T-LGW.

Beam failure recovery mechanism

Example embodiments of the present disclosure relate to beam failure recovery mechanism. According to embodiments of the present disclosure, there are provided an improved solution for reporting candidate beams in serving cells. If a beam failure occurs in a serving cell, the first device determines a candidate beam for beam failure recovery from a plurality of beams in the serving cell based on link qualities of the plurality of beams. The first device also determines a resource configuration for a random access for the beam failure recovery for the first device or a resource to be used for the random access, The first device further generates an indication for indicating a characteristic of the candidate beam or a characteristic of a beam for performing the random access, based on at least one of the determined resource configuration or the determined resource. The first device also transmits an identity of the candidate beam and the indication to a second device. The second device performs the beam failure recovery based on the candidate beam and the characteristic of the candidate beam.

Beam failure recovery mechanism

Example embodiments of the present disclosure relate to beam failure recovery mechanism. According to embodiments of the present disclosure, there are provided an improved solution for reporting candidate beams in serving cells. If a beam failure occurs in a serving cell, the first device determines a candidate beam for beam failure recovery from a plurality of beams in the serving cell based on link qualities of the plurality of beams. The first device also determines a resource configuration for a random access for the beam failure recovery for the first device or a resource to be used for the random access, The first device further generates an indication for indicating a characteristic of the candidate beam or a characteristic of a beam for performing the random access, based on at least one of the determined resource configuration or the determined resource. The first device also transmits an identity of the candidate beam and the indication to a second device. The second device performs the beam failure recovery based on the candidate beam and the characteristic of the candidate beam.

DATA IO AND SERVICE ON DIFFERENT PODS OF A RIC
20220283832 · 2022-09-08 ·

To provide a low latency near RT RIC, some embodiments separate the RIC's functions into several different components that operate on different machines (e.g., execute on VMs or Pods) operating on the same host computer or different host computers. Some embodiments also provide high speed interfaces between these machines. Some or all of these interfaces operate in non-blocking, lockless manner in order to ensure that critical near RT RIC operations (e.g., datapath processes) are not delayed due to multiple requests causing one or more components to stall. In addition, each of these RIC components also has an internal architecture that is designed to operate in a non-blocking manner so that no one process of a component can block the operation of another process of the component. All of these low latency features allow the near RT RIC to serve as a high speed IO between the E2 nodes and the xApps.

DIRECT ACCESS TO HARDWARE ACCELERATOR IN AN O-RAN SYSTEM

Some embodiments provide various methods for offloading operations in an O-RAN (Open Radio Access Network) onto control plane (CP) or edge applications that execute on host computers with hardware accelerators in software defined datacenters (SDDCs). At the CP or edge application operating on a machine executing on a host computer with a hardware accelerator, the method of some embodiments receives data, from an O-RAN E2 unit, to perform an operation. The method uses a driver of the machine to communicate directly with the hardware accelerator to direct the hardware accelerator to perform a set of computations associated with the operation. This driver allows the communication with the hardware accelerator to bypass an intervening set of drivers executing on the host computer between the machine's driver and the hardware accelerator. Through this driver, the application in some embodiments receives the computation results, which it then provides to one or more O-RAN components (e.g., to the E2 unit that provided the data, another E2 unit or another control plane or edge application).

CONFIGURING DIRECT ACCESS TO HARDWARE ACCELERATOR IN AN O-RAN SYSTEM
20220283840 · 2022-09-08 ·

Some embodiments provide various methods for offloading operations in an O-RAN (Open Radio Access Network) onto control plane (CP) or edge applications that execute on host computers with hardware accelerators in software defined datacenters (SDDCs). At the CP or edge application operating on a machine executing on a host computer with a hardware accelerator, the method of some embodiments receives data, from an O-RAN E2 unit, to perform an operation. The method uses a driver of the machine to communicate directly with the hardware accelerator to direct the hardware accelerator to perform a set of computations associated with the operation. This driver allows the communication with the hardware accelerator to bypass an intervening set of drivers executing on the host computer between the machine's driver and the hardware accelerator. Through this driver, the application in some embodiments receives the computation results, which it then provides to one or more O-RAN components (e.g., to the E2 unit that provided the data, another E2 unit or another control plane or edge application).

USING HYPERVISOR TO PROVIDE VIRTUAL HARDWARE ACCELERATORS IN AN O-RAN SYSTEM
20220283841 · 2022-09-08 ·

Some embodiments provide various methods for offloading operations in an O-RAN (Open Radio Access Network) onto control plane (CP) or edge applications that execute on host computers with hardware accelerators in software defined datacenters (SDDCs). At the CP or edge application operating on a machine executing on a host computer with a hardware accelerator, the method of some embodiments receives data, from an O-RAN E2 unit, to perform an operation. The method uses a driver of the machine to communicate directly with the hardware accelerator to direct the hardware accelerator to perform a set of computations associated with the operation. This driver allows the communication with the hardware accelerator to bypass an intervening set of drivers executing on the host computer between the machine's driver and the hardware accelerator. Through this driver, the application in some embodiments receives the computation results, which it then provides to one or more O-RAN components (e.g., to the E2 unit that provided the data, another E2 unit or another control plane or edge application).

RUNNING SERVICES IN SDL OF A RIC

To provide a low latency near RT RIC, some embodiments separate the RIC's functions into several different components that operate on different machines (e.g., execute on VMs or Pods) operating on the same host computer or different host computers. Some embodiments also provide high speed interfaces between these machines. Some or all of these interfaces operate in non-blocking, lockless manner in order to ensure that critical near RT RIC operations (e.g., datapath processes) are not delayed due to multiple requests causing one or more components to stall. In addition, each of these RIC components also has an internal architecture that is designed to operate in a non-blocking manner so that no one process of a component can block the operation of another process of the component. All of these low latency features allow the near RT RIC to serve as a high speed IO between the E2 nodes and the xApps.

RIC WITH A DEDICATED IO THREAD AND MULTIPLE DATA PROCESSING THREADS
20220283843 · 2022-09-08 ·

To provide a low latency near RT RIC, some embodiments separate the RIC's functions into several different components that operate on different machines (e.g., execute on VMs or Pods) operating on the same host computer or different host computers. Some embodiments also provide high speed interfaces between these machines. Some or all of these interfaces operate in non-blocking, lockless manner in order to ensure that critical near RT RIC operations (e.g., datapath processes) are not delayed due to multiple requests causing one or more components to stall. In addition, each of these RIC components also has an internal architecture that is designed to operate in a non-blocking manner so that no one process of a component can block the operation of another process of the component. All of these low latency features allow the near RT RIC to serve as a high speed IO between the E2 nodes and the xApps.