Methods and systems are provided for designing an optimized stack up of layers of a PCB (Printed Circuit Board). A set of constraints is determined for the PCB stack up, where the constraints limit a total number of layers, a number of signal layers, and a thickness of the PCB stack up. Each of the constraints on the PCB stack up is encoded as an equality or an inequality. The set of equalities and inequalities is solved using integer programming techniques to identify an optimal solution to the set of constraints on the PCB stack up, where the optimal solution specifies an arrangement of signaling layers for the PCB. An estimate is generated for impedances and losses for the optimal PCB stack up. The constraints on a PCB stack up are modified when the estimated impedances and losses for the optimal PCB stack up are above a target threshold.

A design program for causing a computer to execute a process including: selecting, based on design data of a printed wiring board, a first transmission line and a second transmission line among transmission lines provided in the printed wiring board; adjusting a first wiring length between a first via in the first transmission line and a third via in the first transmission line, a second wiring length between a second via in the second transmission line and a fourth via in the second transmission line, a length of the first via, a length of the second via, a length of the third via, or a length of the fourth via such that a phase of first crosstalk noise generated between the first via and the second via is inverted between the third via and the fourth via; and outputting the design data corrected based on the adjustment in the board.

A computer-implemented method for designing a printed circuit board including one or more conductive layers is disclosed. The method includes determining one or more conductive elements of each conductive layer, and determining a plurality of thermal zones. Each conductive element is included in a corresponding thermal zone. The method further includes retrieving a clearance ruleset including minimum clearances for the plurality of conductive elements; selecting one conductive element and one other conductive element; determining a distance between the one conductive element and the one other conductive element in three-dimensional space; and recording a spacing violation if the distance between the one conductive element and the one other conductive element is less than the minimum clearance for the one conductive element and the one other conductive element. The method further includes performing thermal analysis of electronic components of each thermal zone and recording a thermal violation based on the thermal analysis.

A method for adjusting a line width and a line gap of a differential signal pair includes performing a new parameter setting step, a distance difference of center calculating step, a reference polygon generating step and a differential signal pair adjusting step. The new parameter setting step is performed to set a new line width and a new line gap of the new differential signal line pair. The distance difference of center calculating step is performed to calculate a difference between an original center distance of the original differential signal line pair and a new center distance of the new differential signal line pair. The reference polygon generating step is performed to generate a reference polygon from an original center line of the original differential signal line pair. The differential signal pair adjusting step is performed to adjust the reference polygon to the new differential signal line pair.

Methods are provided for manufacturing flat devices to be used for forming a shape-retaining non-flat device by deformation of the flat device. Based on the layout of a non-flat device, a layout of a flat device is designed. A method for designing the layout of such a flat device is provided, wherein the method includes inserting mechanical interconnections between pairs of elements to define the position of the elements on a surface of the non-flat device, thus leaving zero or less degrees of freedom for the location of the components. Based on the layout of a flat device thus obtained, the flat device is manufactured and next transformed into the shape-retaining non-flat device by means of a thermoforming process, thereby accurately and reproducibly positioning the elements at a predetermined location on a surface of the non-flat device.

An apparatus and method for selecting a ground capacitor that is connected between a ground of a circuit board included in a battery pack and a vehicle chassis. The apparatus includes a checking module configured to check a ground location on the circuit board; a selecting module configured to select a reference location on the circuit board, based on the ground location checked by the checking module; a calculating module configured to calculate a distance from the reference location selected by the selecting module to a nearest ground location as a reference distance; a computing module configured to compute a reference frequency by using the reference distance calculated by the calculating module; and a choosing module configured to choose a recommended capacitor, based on the reference frequency computed by the computing module.

An apparatus, a recording medium, and a method for generating a control parameter of a screen printer are disclosed. The apparatus includes a memory that stores a simulation model configured to derive predictive inspection information on a printed state of solder paste based on a plurality of control parameters of the screen printer; a communication circuit configured to receive first inspection information on a plurality of solder pastes printed by the screen printer based on a first control parameter, and a processor electrically connected to the memory and the communication circuit. The processor obtains first predictive inspection information by applying the first control parameter to the simulation model, generates a plurality of candidate control parameters based on the first predictive inspection information, determines a plurality of second control parameters among the candidate control parameters, and transmits the plurality of second control parameters to the screen printer via the communication circuit.

A method for adjusting a line width and a line gap of a differential signal pair includes performing a new parameter setting step, a distance difference of center calculating step, a reference polygon generating step and a differential signal pair adjusting step. The new parameter setting step is performed to set a new line width and a new line gap of the new differential signal line pair. The distance difference of center calculating step is performed to calculate a difference between an original center distance of the original differential signal line pair and a new center distance of the new differential signal line pair. The reference polygon generating step is performed to generate a reference polygon from an original center line of the original differential signal line pair. The differential signal pair adjusting step is performed to adjust the reference polygon to the new differential signal line pair.

A system and a method are disclosed for placing hardware components on a printed circuit board (“PCB”) in a way that enables all hardware components on the PCB to be passively cooled without using active cooling systems. Components are selected to be placed onto the PCB and heat metrics for each component is obtained (e.g., from a server). The components are ranked based on the amount of heat that each component generates. A corresponding position for each of the hardware components is determined based on the ranking of the components and the orientation of the PCB. The placement is based on the concept that air having higher temperature rises while air having cooler temperature falls. A representation of the PCB according to corresponding positions of the hardware components may be generated for display.

A first design information of a first printed substrate and a second printed substrate coupled to the first printed substrate via power supply terminals or ground terminals is obtained. Then, first regions are obtained by dividing a region where a power supply wiring layer or a ground wiring layer is formed along a direction in which a power supply current or a ground current flows. Then, second regions are obtained by dividing the plurality of first regions by a plurality of equipotential lines, and a target resistance value of each of the plurality of second regions is calculated based on a target voltage drop between adjacent equipotential lines and a target current value set for each of the power supply terminals or the ground terminals. Then, second design information of the power supply wiring layer or the ground wiring layer is generated based on the target resistance value.