A method of manufacturing a resin multilayer substrate is provided in which a component (3) is incorporated in a stacked body obtained by stacking a plurality of thermoplastic resin sheets (2). The method includes the steps of: softening a first resin sheet (2a) by heating, and pressing the component (3) against the first resin sheet (2a), thereby fixing the component (3) to the first resin sheet (2a); stacking the first resin sheet (2a) on a second resin sheet (2b) having a through hole (14) receiving the component (3) and a third resin sheet (2c) located adjacent to a lower side of the component (3) such that the component (3) is inserted into the through hole (14) and the lower surface of the component (3) faces the third resin sheet (2c); and performing compression bonding by heating and pressurizing the stacked body including these resin sheets (2).

An apparatus and method for manufacturing a power module is provided. The power module includes: a circuit board having a metal pattern formed thereon; a terminal coupled to the circuit board and electrically connected to at least a portion of the metal pattern; a power device chip bonded to the circuit board and electrically connected to at least a portion of the metal pattern and the terminal; and a molding part covering the power device chip and the circuit board. The circuit board includes: a base part comprising an insulating material; a pattern layer disposed on at least one of an upper surface and a lower surface of the base part and providing the metal pattern; and a thin film resistor having a predetermined circuit pattern connecting the metal patterns disposed on the base part to each other.

A circuit board structure includes an inner circuit structure and a first build-up circuit structure. The inner circuit structure includes a core layer having an upper surface and a lower surface, a first patterned circuit layer disposed on the upper surface, a second patterned circuit layer disposed on the lower surface and a conductive through hole connecting the first and the second patterned circuit layers. The first build-up circuit structure at least has a cavity and an inner dielectric layer. The inner dielectric layer has an opening communicating the cavity and a pad of the first patterned circuit layer is located in the opening. A hole diameter of the opening is smaller than a hole diameter of cavity. An inner surface of the inner dielectric layer exposed by the cavity and a top surface of the pad are coplanar or have a height difference.

High-speed interconnects for printed circuit boards and methods for forming the high-speed interconnects are described. A high-speed interconnect may comprise a region of a conductive film having a reduced surface roughness and one or more regions that have been treated for improved bonding with an adjacent insulating layer. Regions of reduced roughness may be used to carry high data rate signals within PCBs. Regions treated for bonding may include a roughened surface, adhesion-promoting chemical treatment, and/or material deposited to improve wettability of the surface and/or adhesion to a cured insulator.

A method of manufacturing a flexible electronic device is provided. The method includes a) filtering a mixture including an electrically conducting nanostructured material through a membrane such that the electrically conducting nanostructured material is deposited on the membrane; b) depositing an elastomeric polymerizable material on the electrically conducting nanostructured material and curing the elastomeric polymerizable material thereby embedding the electrically conducting nanostructured material in an elastomeric polymer thus formed; and c) separating the elastomeric polymer with the embedded electrically conducting nanostructured material from the membrane to obtain the flexible electronic device. Flexible electronic device manufactured by the method, and use of the flexible electronic device are also provided.

A wiring substrate includes a first wiring structure and a second wiring structure. The first wiring structure includes a first insulating layer, which covers a first wiring layer, and a via wiring. A first through hole of the first insulating layer is filled with the via wiring. The second wiring structure includes a second wiring layer and a second insulating layer. The second wiring layer is formed on an upper surface of the first insulating layer and an upper end surface of the via wiring. The second wiring layer partially includes a roughened surface. The second insulating layer is stacked on the upper surface of the first insulating layer and covers the second wiring layer. The second wiring structure has a higher wiring density than the first wiring structure. The roughened surface of the second wiring layer has a smaller surface roughness than the first wiring layer.

A method for manufacturing a resin multilayer board formed from a thermoplastic resin, which method allows for improvement in accuracy of the position of a component relative to the resin multilayer board, is provided. A method for manufacturing a resin multilayer board includes: a step of bonding a component to a pressure-sensitive adhesive layer of a pressure-sensitive adhesive sheet having the pressure-sensitive adhesive layer on a surface thereof; a step of opposing a thermoplastic resin sheet to the pressure-sensitive adhesive layer, and fixing the component bonded to the pressure-sensitive adhesive sheet and the thermoplastic resin sheet to each other by heating; a step of peeling the pressure-sensitive adhesive sheet from the component fixed to the thermoplastic resin sheet; and stacking and thermally welding a plurality of thermoplastic resin sheets including the thermoplastic resin sheet to which the component has been transferred.

A circuit board structure includes an inner circuit structure and a first build-up circuit structure. The inner circuit structure includes a core layer having an upper surface and a lower surface, a first patterned circuit layer disposed on the upper surface, a second patterned circuit layer disposed on the lower surface and a conductive through hole connecting the first and the second patterned circuit layers. The first build-up circuit structure at least has a cavity and an inner dielectric layer. The inner dielectric layer has an opening communicating the cavity and a pad of the first patterned circuit layer is located in the opening. A hole diameter of the opening is smaller than a hole diameter of cavity. An inner surface of the inner dielectric layer exposed by the cavity and a top surface of the pad are coplanar or have a height difference.

Fan-Out Wafer Level Packages (FO-WLPs) having Embedded Ground Plane (EGP) connections are provided. In one embodiment, the FO-WLP includes a molded package body having a frontside and an opposing backside. An EGP and a first preformed EGP connection are contained within the molded package body. The first preformed EGP connection is bonded to the EGP and extends therefrom to the backside of the molded package body. The FO-WLP further includes an electrically-conductive structure, such as an Electromagnetic Interference (EMI) shield, provided on the backside of the molded package body. The electrically-conductive structure is electrically coupled to the EGP through the first preformed EGP connection.

A wiring substrate includes a first wiring structure and a second wiring structure. The first wiring structure includes a first insulating layer, which covers a first wiring layer, and a via wiring. A first through hole of the first insulating layer is filled with the via wiring. The second wiring structure includes a second wiring layer and a second insulating layer. The second wiring layer is formed on an upper surface of the first insulating layer and an upper end surface of the via wiring. The second wiring layer partially includes a roughened surface. The second insulating layer is stacked on the upper surface of the first insulating layer and covers the second wiring layer. The second wiring structure has a higher wiring density than the first wiring structure. The roughened surface of the second wiring layer has a smaller surface roughness than the first wiring layer.