A resin multilayer substrate includes a multilayer body including resin layers and adhesive layers that are laminated, via conductors in the resin layers, and bonding portions in the adhesive layers. The bonding portion is connected to the via conductor. One of the resin layer and the adhesive layer is a gas high-permeable layer having a higher gas permeability than the other one. The bonding portion includes an organic substance, or has a higher void content rate per unit plane sectional area than the via conductor. At least a portion of each of the bonding portions contacts the gas high-permeable layers.

Filing a plated through-hole of a circuit board with solder is facilitated by an apparatus which includes a wire solder assembly and a controller. The wire solder assembly includes a wire probe sized to extend into the plated through-hole from one side of the circuit board, and a solder block associated with the wire probe so that the probe passes through the solder block. The controller controls heating of the wire probe, when the wire probe is operatively inserted into the plated through-hole, by passing a current through the wire probe. The heating of the wire probe heats a conductive plating of the plated through-hole and melts the solder block. The heating of the conductive plating and the melting of the solder block causes the solder to migrate into the plated through-hole by capillary action to fill the plated through-hole with the solder.

A component carrier has a stack including a plurality of electrically insulating layer structures and at least one electrically conductive layer structure, wherein two of the at least two electrically insulating layer structures form a dielectric double layer made of two different materials; a through-hole extending through the double dielectric layer; and an electrically conductive material filling at least a part of the through-hole. A method of manufacturing a component carrier is also disclosed.

A wiring substrate includes an insulating layer having through holes, a first conductor layer formed on first surface of the insulating layer, a second conductor layer formed on second surface of the insulting layer on the opposite side, and interlayer connection conductors formed in the through holes through the insulating layer and connecting the first and second conductor layers. The insulating layer is formed such that the though holes include first and second groups of through holes and that the through holes in the second group have inner walls covered with non-conductive resin, and the interlayer conductors includes first interlayer conductors each including a plating film formed in the first group of through holes, and second interlayer conductors each including a plating film formed in the second group of through holes such that minimum distance between the second interlayer conductors is smaller than minimum distance between the first interlayer conductors.

A component carrier includes an electrically insulating layer structure, a first electrically conductive layer structure, a second electrically conductive layer structure, and a laser through-hole with an electrically conductive medium filling at least part of the through-hole. The first electrically conductive layer structure covers a first side of the electrically insulating layer structure and has a first window extending through the first electrically conductive layer structure formed by etching using a conformal mask. The second electrically conductive layer structure covers an opposed side of the electrically insulating layer structure and has a second window extending through the second electrically conductive layer structure formed by etching using a conformal mask. The laser through-hole extends through the electrically insulating layer structure. At least a portion of at least one sidewall of the electrically conductive layer structures delimiting the windows is tapered.

A method is provided for forming a printed circuit board (PCB) assembly. The method may include drilling a first plurality of vias having a first diameter in a PCB and filling the first plurality of vias to form a first plurality of plated or filled vias. The method may also include drilling a second plurality of vias having a second diameter in the PCB, and filling the second plurality of vias to form a second plurality of plated or filled vias. The first plurality of plated or filled vias is mixed with the second plurality of plated or filled vias such that the spacing between the first plurality of plated or filled vias and the second plurality of plated or filled vias is less than the first diameter and the second diameter.

A method for producing a sandwich arrangement consisting of a first component having a contact surface A, a second component having a contact surface D and a solder located between said contact surfaces A and D,

wherein the solder is produced by melting a solder deposit that is arranged between the two components and connected at the contact surface A or D to one of the components, followed by cooling of the molten solder to below its solidification temperature,
wherein the solder deposit is produced previously by melting a solder preform that is fixed to the relevant contact surface A or D by means of an applied fixing agent from a fixing agent composition, followed by cooling of the molten solder to below its solidification temperature, and
wherein the solder deposit is arranged with its free contact surface facing the corresponding contact surface D or A of the as of yet unconnected component, wherein the fixing agent composition consists of
0 to 97 wt. % (weight %) of at least one solvent selected from the group consisting of water and organic solvents boiling at 285 C.,
3 to 100 wt. % of at least one M1 material selected from the group consisting of (i) thermoplastic organic polymers that are meltable between 30 and 180 C. and (ii) non-polymeric organic compounds with no acidic groups that are meltable between 30 and 180 C.,
0 to 20 wt. % of at least one M2 material selected from the group consisting of (iii) organic polymers that are not meltable between 30 and 180 C. and (iv) non-polymeric organic compounds with no acidic groups that are not meltable between 30 and 180 C. and not having a boiling point or having a boiling point above 285 C., and
0 to 30 wt. % of one or more inorganic solid fillers, and
wherein the sum of the surface sections that are provided with the fixing agent, of the contact surfaces A and B or C and D that upon placing the solder preform together form a common overlapping area, in the presence of one or more components (i) in the at least one M1 material is 1500 m.sup.2 to 50 area % of the common overlapping area, while, when only one or more of the components (ii) are present in the at least one M1 material said sum is 1500 m.sup.2 to 100 area % of the common overlapping area.

Disclosed herein is a bottom-up electrolytic via plating method wherein a first carrier substrate and a second substrate having at least one through-via are temporarily bonded together. The method includes applying a seed layer on a surface of the first substrate, forming a surface modification layer on the seed layer or the second substrate, bonding the second substrate to the first substrate with the surface modification layer to create an assembly wherein the seed layer and the surface modification layer are disposed between the first and second substrates, applying conductive material to the through-via, removing the second substrate having the through-via containing conductive material from the assembly.

A printed wiring board in the present disclosure includes a core layer, a first buildup layer, a second buildup layer, and a through hole. The core layer has a conductor circuit located on a surface of an insulator. The first buildup layer containing a first resin is laminated on a surface of the core layer. The second buildup layer containing a second resin is laminated on a surface of the first buildup layer. The through hole extends through the core layer, the first buildup layer, and the second buildup layer. The first resin and the second resin are different from each other. The second buildup layer includes a plurality of filled vias filled with a conductor which are located around a circumference of an opening of the through hole.

A method of manufacturing a circuit substrate includes forming, in an insulating substrate and circuit patterns that are provided on a first surface and a second surface of the insulating substrate, a through-hole penetrating the insulating substrate and the circuit patterns, where the circuit patterns contain Cu as a main component. The method includes filling, in the through-hole, an electrically conductive paste that is a melting-point shift electrically conductive paste including SnBi solder powder, Cu powder, and resin, and forming a protrusion obtained by causing the electrically conductive paste to protrude from the through-hole. The method further includes performing pressure treatment on the protrusion near the through-hole; and performing heat treatment on the insulating substrate whose protrusion is subjected to the pressure treatment and causing the circuit patterns and the electrically conductive paste to be electrically connected with each other.