A package device and a manufacturing method thereof are provided. The package device includes a redistribution layer including a first dielectric layer, a conductive layer, and a second dielectric layer. The conductive layer is disposed between the first dielectric layer and the second dielectric layer. The redistribution layer has a test mark, the test mark includes a plurality of conductive patterns formed of the conductive layer, and the conductive patterns are arranged in a ring shape.

A method of mass spectral analysis in an analytical electrostatic trap (14) is disclosed. The electrostatic trap (14) defines an electrostatic field volume and includes trap electrodes having static and non-ramped potentials. The method comprises injecting a continuous ion beam into the electrostatic field volume.

A method of making a printed circuit board includes a step of providing a double-sided plate that is an insulating substrate having conductive layers on respective surfaces thereof, a first coating step of coating a first surface of the double-sided plate with a first photosensitive resin film, a second coating step of coating a second surface of the double-sided plate with a second photosensitive resin film, a first exposure step of exposing the photosensitive resin film coating the first surface after the first and second coating steps, and a second exposure step of exposing the photosensitive resin film coating the second surface after the first exposure step, wherein a maximum depth of a depression in an outermost surface of the second photosensitive resin film used in the second exposure step is less than 1.0 μm.

A resin composition is provided. The resin composition comprises the following components: (A) a halogen-free epoxy resin; (B) a hardener; and (C) a phosphorus-containing phenolic resin of the following formula (I): ##STR00001##
wherein m, n, l, R.sub.1, and R.sub.2 are as defined in the specification.

A quantum mechanical circuit includes a substrate; a first electrical conductor and a second electrical conductor provided on the substrate and spaced apart to provide a gap therebetween; and a third electrical conductor to electrically connect the first electrical conductor and the second electrical conductor. The third electrical conductor is a poor thermal conductor.

A quantum mechanical circuit includes a substrate; a first electrical conductor and a second electrical conductor provided on the substrate and spaced apart to provide a gap therebetween; and a third electrical conductor to electrically connect the first electrical conductor and the second electrical conductor. The third electrical conductor is a poor thermal conductor.

A method for preparing a ceramic copper clad laminate is provided, including following steps: providing a copper material; forming a copper oxide layer on a surface of the copper material; thermally treating the copper material on which the copper oxide layer is formed, to diffuse oxygen atoms in the copper material; removing the copper oxide layer on the thermally treated copper material; and soldering the copper-oxide-layer-removed copper material to a ceramic substrate to obtain a ceramic copper clad laminate.

[Object]

To provide a copper clad laminate that is capable of achieving a good volume resistivity at an electroless copper plating layer of a low dielectric resin film while suppressing a transmission loss when being applied to a flexible circuit board, and a method for producing the copper clad laminate.

[Solving Means]

A copper clad laminate of the present invention includes a low dielectric resin film having a relative permittivity of 3.5 or lower and a dissipation factor of 0.008 or lower at a frequency of 10 GHz, and an electroless copper plating layer laminated on at least one surface of the low dielectric resin film. An Ni content in the electroless copper plating layer is 0.01 to 1.2 wt %, and the electroless copper plating layer has a volume resistivity of 6.0 μΩ.Math.cm or lower.

A surface treated copper foil 1 includes a copper foil 2, and a first surface treatment layer 3 formed on one surface of the copper foil 2. The first surface treatment layer 3 of the surface treated copper foil 1 has L* of a CIE L*a*b* color space of 44.0 to 84.0. A copper clad laminate 10 includes the surface treated copper foil 1 and an insulating substrate 11 adhered to a surface of the surface treated copper foil 1 opposite to the first surface treatment layer 3.

Provided are flexible interconnect circuit assemblies and methods of fabricating thereof. In some examples, a flexible interconnect circuit comprises multiple circuit portions, which are monolithically integrated. During the fabrication, some of these circuit portions are folded relative to other portions, forming a stack in each fold. For example, the initial orientation of these portions can be selected such that smaller sheets can be used for circuit fabrication. The portions are then unfolded into the final design configuration. In some examples, the assembly also comprises a bonding film and a temporary support film attached to the bonding film such that the two circuit portions at least partially overlap with the bonding film and are positioned between the bonding film and temporary support film. In some examples, at least some circuit portions extend past the boundary of the bonding film and are coupled to connectors.