A substrate connection member according to various embodiments of the present invention can comprise a printed circuit board which has a plurality of layers that are stacked and which comprises a front surface, a rear surface, and a side surface encompassing the front surface and the rear surface. The printed circuit board can comprise: an opening part which encompasses a partial region of the printed circuit board and which is penetratingly formed from the front surface to the rear surface; at least one bridge connected between the partial region and the printed circuit board by crossing at least a portion of the opening part; and at least one through-hole wire formed in the partial region from the front surface to the rear surface, wherein the inner surface of the opening part and the side surface of the bridge can be formed from a conductive member. Other various embodiments, in addition to the embodiments disclosed in the present invention, are possible.

A manufacturing method of a carrier structure includes: A build-up circuit layer is formed on a carrier. The build-up circuit layer includes at least one first circuit layer, at least one first dielectric layer, a second circuit layer, a second dielectric layer, and a plurality of conductive vias. The first circuit layer is located on the carrier and includes at least one first pad, which is disposed relative to at least one through hole of the carrier. The first dielectric layer is located on the first circuit layer. The second circuit layer is located on the first dielectric layer and includes at least one second pad. The second dielectric layer is located on the second circuit layer and includes at least one opening exposing the second pad. The conductive via penetrates the first dielectric layer and is electrically connected to the first circuit layer and the second circuit layer.

In one embodiment, an automated high-speed X-ray inspection system may generate a first X-ray image of an inspected sample at a first direction substantially orthogonal to a plane of the inspected sample. The first X-ray image may be a high-resolution grayscale image. The system may identify one or more elements of interest of the inspected sample based on the first X-ray image. The first X-ray image may include interfering elements that interfere with the one or more elements of interest in the first X-ray image. The system may determine one or more first features associated with respective elements of interest based on variations of grayscale values in the first X-ray images. The system may determine whether one or more defects are associated with the respective elements of interest based on the one or more first features associated with the element of interest.

The manufacturing method includes (a) preparing first printed circuit board and second printed circuit board, the first printed circuit board being provided with a plurality of first terminals, the second printed circuit board being provided with a plurality of second terminals, and the first terminals or the second terminals being coated with solders; and (b) connecting the first terminals and the second terminals, respectively, via respective solders by performing thermocompression on connecting portions of the first printed circuit board and the second printed circuit board. Each second terminal includes a first end portion and a second end portion in a long axis direction, and in the step (b), pressure is applied to each second terminal such that the height of each of the first end portion and second end portion is larger than the height in another portion of the second terminal.

A circuit board with via capacitor structure is introduced herein, including a base, a deposition layer, disposed on the base, having at least a via in the deposition layer, at least a thin film capacitor, each thin film capacitor disposed in each via, each thin film capacitor having a body, a second terminal, and a first terminal, the second terminal and the first terminal located on two opposite sides of the body; at least a first electrode, each first electrode electrically connected to the first terminal of each thin film capacitor; and at least a second electrode, each second electrode electrically connected to the second terminal of each thin film capacitor.

Circuit board includes conductive plate, core dielectric layer, metallization layer, first build-up stack, second build-up stack. Conductive plate has channels extending from top surface to bottom surface. Core dielectric layer extends on covering top surface and side surfaces of conductive plate. Metallization layer extends on core dielectric layer and within channels of conductive plate. Core dielectric layer insulates metallization layer from conductive plate. First build-up stack is disposed on top surface of conductive plate and includes conductive layers alternately stacked with dielectric layers. Conductive layers electrically connect to metallization layer. Second build-up stack is disposed on bottom surface of conductive plate. Second build-up stack includes bottommost dielectric layer and bottommost conductive layer. Bottommost dielectric layer covers bottom surface of conductive plate. Bottommost conductive layer is disposed on bottommost dielectric layer and electrically connects to metallization layer. First build-up stack includes more conductive and dielectric layers than second build-up stack.

A circuit board according to an embodiment includes a first insulating layer; a second insulating layer disposed on an upper surface of the first insulating layer; a first circuit pattern buried in a lower region of the first insulating layer and including a first via pad; a second circuit pattern disposed between the first insulating layer and the second insulating layer and including a second via pad; a third circuit pattern buried in an upper region of the second insulating layer and including a third via pad; a first via disposed in the first insulating layer and connecting the first via pad and the second via pad; and a second via disposed in the second insulating layer and connecting the second via pad and the third via pad, and wherein at least one of an upper surface and a lower surface of the second via includes a convex portion in an upward or downward direction.

A printed circuit board includes: an insulating layer including a cavity formed therein, the cavity being recessed into the insulating layer from a top surface of the insulating layer; a first circuit layer formed inside the insulating layer such that a portion of the first circuit layer is disposed within the cavity; a second circuit layer disposed above the insulating layer; a first surface-treated layer disposed above the portion of the first circuit layer disposed within the cavity; and a second surface-treated layer disposed above the second circuit layer.

A printed circuit board includes: an insulating layer including a cavity formed therein, the cavity being recessed into the insulating layer from a top surface of the insulating layer; a first circuit layer formed inside the insulating layer such that a portion of the first circuit layer is disposed within the cavity; a second circuit layer disposed above the insulating layer; a first surface-treated layer disposed above the portion of the first circuit layer disposed within the cavity; and a second surface-treated layer disposed above the second circuit layer.

Various embodiments of a sealed package and a method of forming such package are disclosed. The package can include a non-conductive substrate that includes a cavity disposed in a first major surface. A cover layer can be disposed over the cavity and attached to the first major surface of the non-conductive substrate to form a sealed enclosure. The sealed package can also include a feedthrough that includes a via between a recessed surface of the cavity and a second major surface of the substrate, and a conductive material disposed in the via. An external contact can be disposed over the via on the second major surface of the non-conductive substrate, where the external contact is electrically connected to the conductive material disposed in the via. The sealed package can also include an electronic device disposed within the sealed enclosure that is electrically connected to the external contact.