A component-embedded substrate includes: a plurality of insulating layers each including a wiring pattern formed on one surface; an embedded component including a connection terminal; and a plurality of vias that electrically connect the connection terminal to the wiring patterns adjacent to each other in a lamination direction. The plurality of insulating layers is laminated on the connection terminal. Each of the plurality of vias is composed of a via hole formed in the respective insulating layer of the plurality of the insulating layers and a conductive material provided in the via hole. One of the plurality of vias is a connection via directly connected to the connection terminal. Another of the plurality of vias is a first adjacent via adjacent to the connection via in the lamination direction. The first adjacent via is connected to the wiring pattern formed on a surface of a top insulating layer.

Lighting device for a motor vehicle including a light source and/or an optical part. A substrate including electrical tracks, the light source and/or optical part being fastened to the substrate, and a part forming an electrical ground for the electrical tracks. The substrate includes a cut-out forming a tab, electrical tracks of the substrate extending onto the tab, at least one of the tracks on the tab making electrical contact with the ground-forming part.

The present disclosure discloses a multilayer circuit board comprising a plurality of metal layers, a blind via and/or a buried via, the multilayer circuit board is capable of transmitting signal between the different metal layers. The blind via has a pad on a non-opening side of the blind via. An upper or lower layer metal layer on the non-opening side of the blind via adjacent to the blind via has a first hole which is located in a position corresponding to the pad on the non-opening side of the blind via in a depth direction of the blind via; and/or an upper and/or lower layer adjacent to the buried via has a second hole which is located in a position corresponding to the pad of an upper and/or lower orifice of the buried via in a depth direction of the buried via.

A method for producing a metal-ceramic substrate with electrically conductive vias includes: attaching a first metal layer in a planar manner to a first surface side of a ceramic layer; after attaching the first metal layer, introducing a copper hydroxide or copper acetate brine into holes in the ceramic layer delimiting a via, to form an assembly; converting the copper hydroxide or copper acetate brine into copper oxide; subjecting the assembly to a high-temperature step above 500° C. in which the copper oxide forms a copper body in the holes; and after converting the copper hydroxide or copper acetate brine into the copper oxide, attaching a second metal layer in a planar manner to a second surface side of the ceramic layer opposite the first surface side. The copper body produces an electrically conductive connection between the first and the second metal layers.

A stackable via package includes a substrate having an upper surface and a trace on the upper surface, the trace including a terminal. A solder ball is on the terminal. The solder ball has a solder ball diameter A and a solder ball height D. A via aperture is formed in a package body enclosing the solder ball to expose the solder ball. The via aperture includes a via bottom having a via bottom diameter B and a via bottom height C from the upper surface of the substrate, where A<B and 0=<C<1/2×D. The shape of the via aperture prevents solder deformation of the solder column formed from the solder ball as well as prevents solder bridging between adjacent solder columns.

A method for manufacturing a wiring circuit board that is a double-sided wiring circuit board includes a first step of preparing a laminate and a second step. The laminate includes a metal core layer, insulating layer, and conductor layers. The insulating layer has a region and an opening that are adjacent to each other. The insulating layer has a region including a part facing the region in a thickness direction, and an opening adjacent to the region. The conductor layer includes a wiring portion and a conductive portion. The conductor layer includes a wiring portion and a conductive portion. In the second step, the first and second etching treatments for etching the metal core layer through the openings are carried out to form a via portion having a periphery surrounded by a space, extending between the regions, and connected to the conductive portions.

Aspects include a hybrid socket dynamic warp indicator for socket connector systems and methods of using the same to measure the warpage of a printed circuit board assembly. The method can include providing a printed circuit board having a plurality of pads and a socket. A warp indicator having a plurality of solder joint connections and a resistor array is electrically coupled to the printed circuit board to build a printed circuit board assembly. The printed circuit board assembly is subjected to a thermal event. A resistance across the resistor array is measured after the thermal event. A number of separations between one or more pads of the printed circuit board and one or more solder joint connections of the warp indicator is determined based on a change in the resistance. A defective warpage condition for the socket is determined based on the number of separations.

A circuit board according to an embodiment includes an insulating layer including an upper surface and a lower surface, and having a via hole passing through the upper surface and the lower surface in a thickness direction from the upper surface to the lower surface, wherein the via hole includes: a first via part adjacent to the upper surface and having a constant inclination angle along the thickness direction; a second via part adjacent to the lower surface and having a constant inclination angle along the vertical direction; and a third via part disposed between the first via part and the second via part and having an inclination angle different from an inclination angle of the first via part and an inclination angle of the second via part.

A package substrate according to an embodiment includes an insulating layer; a first outer circuit pattern disposed on an upper surface of the insulating layer; a second outer circuit pattern disposed under a lower surface of the insulating layer; a first connection portion disposed on an upper surface of a first-first circuit pattern of the first outer circuit pattern; a first contact portion disposed on the first connection portion; a first device disposed on the first connection portion through the first contact portion; a second contact portion disposed under a lower surface of a second-first circuit pattern of the second outer circuit pattern; a second device attached to the second-first circuit pattern through the second contact portion; and a second connection portion disposed under a lower surface of a second-second circuit pattern of the second outer circuit pattern; wherein the first connection portion is disposed with a first width and a first interval, and wherein the second connection portion is disposed with a second width greater than the first width and a second interval greater than the first interval.

A package substrate according to an embodiment includes an insulating layer; a first outer circuit pattern disposed on an upper surface of the insulating layer; a second outer circuit pattern disposed under a lower surface of the insulating layer; a first connection portion disposed on an upper surface of a first-first circuit pattern of the first outer circuit pattern; a first contact portion disposed on the first connection portion; a first device disposed on the first connection portion through the first contact portion; a second contact portion disposed under a lower surface of a second-first circuit pattern of the second outer circuit pattern; a second device attached to the second-first circuit pattern through the second contact portion; and a second connection portion disposed under a lower surface of a second-second circuit pattern of the second outer circuit pattern; wherein the first connection portion is disposed with a first width and a first interval, and wherein the second connection portion is disposed with a second width greater than the first width and a second interval greater than the first interval.