A package substrate according to an embodiment includes an insulating layer; a first outer circuit pattern disposed on an upper surface of the insulating layer; a second outer circuit pattern disposed under a lower surface of the insulating layer; a first connection portion disposed on an upper surface of a first-first circuit pattern of the first outer circuit pattern; a first contact portion disposed on the first connection portion; a first device disposed on the first connection portion through the first contact portion; a second contact portion disposed under a lower surface of a second-first circuit pattern of the second outer circuit pattern; a second device attached to the second-first circuit pattern through the second contact portion; and a second connection portion disposed under a lower surface of a second-second circuit pattern of the second outer circuit pattern; wherein the first connection portion is disposed with a first width and a first interval, and wherein the second connection portion is disposed with a second width greater than the first width and a second interval greater than the first interval.

In a transmission line, a thickness of a second section is smaller than that of a first section and of a third section. A center of the second section is above a center of the first section and a center of the third section in a laminated body up-down direction. A distance between a second signal conductor layer and a neutral plane of the second section is shorter than a distance between a first signal conductor layer and a neutral plane of the second section and a distance between a third signal conductor layer and a neutral plane of the second section in the laminated body up-down direction. A length of the second signal conductor layer between first and second interlayer connection conductors is equal to or less than about ½ of a wavelength of a high-frequency signal transmitted by the transmission line.

A component carrier includes a stack with an electrically conductive layer structure and an electrically insulating layer structure. The electrically conductive layer structure having a first plating structure and a pillar. The pillar has a seed layer portion on the first plating structure and a second plating structure on the seed layer portion. A method of manufacturing such a component carrier and an arrangement including such a component carrier are also disclosed.

The present invention relates to a support-attached resin film for an interlayer insulating layer, including a support, and a resin composition layer formed on one side surface of the support in which the support has particles exposed on the one side surface, and an average maximum height of exposed portions of the particles is 1.0 μm or less, or the support has no particles exposed on the one side surface, a multilayer printed wiring board using the support-attached resin film for an interlayer insulating layer, and the multilayer printed-wiring board.

A flexible circuit board includes liquid crystal polymer (LCP) layers and metal layers including circuit routes. Each of the LCP layers includes via structures. The metal layers and the LCP layers are alternatively stacked to form a multi-layer structure. Adjacent metal layers are electrically connected through the via structures. Some via structures of different LCP layers are substantially aligned with one another to form a stack of via structures. Each of the via structures includes openings filled with conductive material. The size of the opening fulfils the following equation: Vb≥cos(Bh/Vh)*Vt/k*2, where Vb is a diameter of a smaller aperture, Vt is a diameter of a bigger aperture, Vh is a combined thickness of a LCP layer and a metal layer, Bh is a thickness of a LCP layer and k is a tensile modulus.

A testing substrate includes a first build-up structure and a ceramic substrate. The ceramic substrate is arranged on the first build-up structure. The first bonding interface between the first build-up structure and the ceramic substrate includes a dielectric-to-dielectric bonding interface and a metal-to-metal bonding interface. A manufacturing method of a testing substrate and a probe card are also provided.

A wiring board includes a resin insulating layer having a component mounting surface, first connection pads formed on the component mounting surface of the resin insulating layer, second connection pads formed on the component mounting surface of the resin insulating layer such that the second connection pads are surrounding the first connection pads, and a protruding part including a metal material and formed on the component mounting surface of the resin insulating layer such that a portion of the protruding part is embedded in the resin insulating layer and that the protruding part is positioned between the first connection pads and the second connection pads and surrounding the first connection pads.

An embedded module according to the present invention includes a base substrate having a multi-layer wiring, at least two semiconductor chip elements having different element thicknesses, each of the semiconductor chip element having a first surface fixed to the base substrate and having a connection part on a second surface, an insulating photosensitive resin layer enclosing the semiconductor chip elements on the base substrate and being formed by a first wiring photo via, a second wiring photo via, and a wiring, the first wiring photo via electrically connected to the connection part of the semiconductor chip elements, the second wiring photo via arranged at the outer periphery of each of the semiconductor chip elements and electrically connected to a connection part of the base substrate, the wiring arranged so as to be orthogonal to and electrically connected to the first wiring photo via and the second wiring photo via.

A method for manufacturing a circuit board is disclosed. An inner wiring base board with a first opening is provided. A base board is fixed in the first opening, and a first wiring base board and a second wiring base board are pressed on opposite surfaces of the inner wiring base board. The base board is made of ceramic and has a high light reflectivity of 92% to 97%. A first conductor layer and a second conductor layer are formed on opposite surfaces of the laminated structure. The first conductor layer includes a plurality of connecting pads on the base board. A solder mask is formed on an outer side of the first conductor layer, the solder mask has a high light reflectivity of 92% to 95%, and the base board is exposed outside the solder mask.

A wiring substrate includes a first insulating layer with a first opening, a second insulating layer with a second opening, a high-frequency wiring layer, a first wiring layer, a second wiring layer, and a plurality of conductive pillars. The high-frequency wiring layer including a high-frequency trace is sandwiched between the first insulating layer and the second insulating layer. The first opening and the second opening expose two sides of the high-frequency trace respectively. The high-frequency trace has a smooth surface which is not covered by the first insulating layer and the second insulating layer and has the roughness ranging between 0.1 and 2 μm. The first insulating layer and the second insulating layer are all located between the first wiring layer and the second wiring layer. The conductive pillars are disposed in the second insulating layer and connected to the high-frequency trace.