There is a method of manufacturing a multilayer wiring board including: alternately stacking wiring layers and insulating layers; stacking a reinforcing sheet on one surface of the resulting multilayer laminate with a soluble adhesive layer therebetween, wherein an unoccupied region without the soluble adhesive layer is provided within a facing area where the reinforcing sheet faces the multilayer laminate; allowing a liquid capable of dissolving the soluble adhesive layer to infiltrate the unoccupied region to dissolve or soften the soluble adhesive layer; and releasing the reinforcing sheet from the multilayer laminate at the soluble adhesive layer. This method enables the multilayer wiring layer to be reinforced to generate no large local warpage, thereby improving the reliable connection and the surface flatness (coplanarity) of the multilayer wiring layer. The used reinforcing sheet can be released in a significantly short time, while minimizing the stress applied to the multilayer laminate.

A printed circuit board can include a substrate layer, a first metal layer disposed over the substrate layer, a core layer disposed over the first metal layer, and a second metal layer disposed over the core layer, where the core layer defines a closed cavity between the first and second metal layers. Optionally, the cavity is filled with air and operates as an antenna.

Techniques and mechanisms for providing anisotropic etching of a metallization layer of a substrate. In an embodiment, the metallization layer includes grains of a conductor, wherein a first average grain size and a second average grain size correspond, respectively, to a first sub-layer and a second sub-layer of the metallization layer. The first sub-layer and the second sub-layer each span at least 5% of a thickness of the metallization layer. A difference between the first average grain size and the second average grain size is at least 10% of the first average grain size. In another embodiment, a first condition of metallization processing contributes to grains of the first sub-layer being relatively large, wherein an alternative condition of metallization processing contributes to grains of the second sub-layer being relatively small. A grain size gradient across a thickness of the metallization layer facilitates etching processes being anisotropic.

A multilayer substrate includes a pair of first capacitor electrodes, a pair of second capacitor electrodes, and a dielectric substrate. Electrodes of the pair of first capacitor electrodes are disposed in dielectric substrate so as to face each other in a thickness direction of the dielectric substrate. Electrodes of the pair of second capacitor electrodes are disposed in the dielectric substrate so as to face each other in the thickness direction. A first element and a second element that are disposed in or on the dielectric substrate, and the pair of second capacitor electrodes, the pair of first capacitor electrodes, and a ground electrode that are disposed in the dielectric substrate are arranged in the stated order in the thickness direction. The pair of second capacitor electrodes at least partially overlaps the pair of first capacitor electrodes when viewed in plan in the thickness direction.

A multilayer substrate includes a pair of first capacitor electrodes, a pair of second capacitor electrodes, and a dielectric substrate. Electrodes of the pair of first capacitor electrodes are disposed in dielectric substrate so as to face each other in a thickness direction of the dielectric substrate. Electrodes of the pair of second capacitor electrodes are disposed in the dielectric substrate so as to face each other in the thickness direction. A first element and a second element that are disposed in or on the dielectric substrate, and the pair of second capacitor electrodes, the pair of first capacitor electrodes, and a ground electrode that are disposed in the dielectric substrate are arranged in the stated order in the thickness direction. The pair of second capacitor electrodes at least partially overlaps the pair of first capacitor electrodes when viewed in plan in the thickness direction.

A module of an embodiment of the present disclosure includes a first substrate including a first wiring pattern and a second substrate having a second wiring pattern with a wiring density different from that of the first wiring pattern, in which the second substrate is bonded to the first substrate. At least one of the first substrate or the second substrate has visible light transmittance.

A mini smart card and a method of manufacturing the mini smart card are introduced. The method includes disposing bilayered print layers on a top side and a bottom side of a circuit layer, respectively; performing a heat-compression treatment and then a printing treatment on the circuit layer and the bilayered print layers; removing surface layers from the bilayered print layers; and disposing transparent protective layers on the bilayered print layers, respectively. The bilayered print layers are prevented from deforming under the heat generated during the printing treatment. Removal of the surface layers from the bilayered print layers effectively reduces the thickness of the mini smart card.

A wiring board includes: an insulating layer; and a connection terminal formed on the insulating layer. The connection terminal includes a first metal layer laminated on the insulating layer, a second metal layer laminated on the first metal layer, a metal pad laminated on the second metal layer, and a surface treatment layer that covers an upper surface and a side surface of the pad and that is in contact with the upper surface of the insulating layer. An end portion of the second metal layer is in contact with the surface treatment layer, and an end portion of the first metal layer is positioned closer to a center side of the pad than the end portion of the second metal layer is to form a gap between the end portion of the first metal layer and the surface treatment layer.

A wiring board, comprising: wiring patterns that are buried in the wiring board, in which a region positioned between wiring patterns disposed in an in-plane direction of the same plane has an elastic modulus at 140° C. equal to or less than 0.1 MPa, and a dielectric loss tangent is equal to or less than 0.006.

A method of manufacturing a multilayer board includes forming conductor patterns on four or more insulating base material layers, forming a multilayer body by stacking the insulating base material layers in a state in which the conductor patterns face each other with prepreg layers therebetween, and heat-pressing the multilayer body. In a state before the step of heat-pressing, among the prepreg layers, a thickness of an outermost prepreg layer is larger than a thickness of a prepreg layer other than the outermost prepreg layer.