An integrated circuit includes: a cell array including a plurality of memory cells in a plurality of first rows and a plurality of write assistance cells in at least one second row; a plurality of word lines respectively extending on the plurality of first rows; at least one write assistance line respectively extending on the at least one second row; and a row driver connected to the plurality of word lines and the at least one write assistance line, the row driver being configured to, during a write operation, activate at least one of the plurality of write assistance cells through the at least one write assistance line, wherein each of the plurality of write assistance cells includes the same transistor configuration as each of the plurality of memory cells and has the same footprint as each of the plurality of memory cells.

An integrated circuit device includes an active area extending in a first direction on a substrate and a gate line extending in a second direction intersecting with the first direction to intersect with the active area. The gate line comprises a first sidewall and a second sidewall opposite to each other. The first sidewall has a convex shape. The second sidewall has a concave shape.

A semiconductor device and method of fabricating thereof where the device includes a fin structure between a first isolation region and a second isolation region. A first source/drain feature is formed over a recessed portion of the first fin structure. The first source/drain feature interfaces a top surface of the first isolation region for a first distance and interfaces the top surface of the second isolation region for a second distance. The first distance is different than the second distance. The source/drain feature is offset in a direction.

Memory devices are provided. In an embodiment, a memory device includes a static random access memory (SRAM) array. The SRAM array includes a static random access memory (SRAM) array. The SRAM array includes a first subarray including a plurality of first SRAM cells and a second subarray including a plurality of second SRAM cells. Each n-type transistor in the plurality of first SRAM cells includes a first work function stack and each n-type transistor in the plurality of second SRAM cells includes a second work function stack different from the first work function stack.

A includes depositing a gate electrode layer over a semiconductor substrate; patterning the gate electrode layer into a first gate electrode and a gate electrode extending portion; forming a first gate spacer alongside the first gate electrode; patterning the gate electrode extending portion into a second gate electrode after forming the first gate spacer; and forming a second gate spacer alongside the second gate electrode and a third gate spacer around the first spacer.

A device includes a semiconductor substrate, a semiconductor fin, a gate structure, a first source/drain epitaxy structure, a second source/drain epitaxy structure, a first dielectric fin sidewall structure, a second dielectric fin sidewall structure. The semiconductor fin is over the semiconductor substrate. The semiconductor fin includes a channel portion and recessed portions on opposite sides of the channel portion. The gate structure is over the channel portion of the semiconductor fin. The first source/drain epitaxy structure and the second source/drain epitaxy structure are over the recessed portions of the semiconductor fin, respectively. The first source/drain epitaxy structure has a round surface. The first dielectric fin sidewall structure and the second dielectric fin sidewall structure are on opposite sides of the first source/drain epitaxy structure. The round surface of the first source/drain epitaxy structure is directly above the first dielectric fin sidewall structure.

The invention provides a semiconductor layout pattern, the semiconductor layout pattern includes a substrate, a plurality of ternary content addressable memories (TCAM) are arranged on the substrate, the layout of at least two TCAM is mirror symmetric with each other along an axis of symmetry, and the two TCAM are connected to the same search line (SL) together.

Semiconductor device is provided. The semiconductor device includes a base substrate including a first region, a second region, and a third region, a first doped layer in the base substrate at the first region and a second doped layer in the base substrate at the third region, a first gate structure on the base substrate at the second region, a first dielectric layer on the base substrate, a first conductive layer on the first conductive layer and the second doped layer, a second conductive layer on a surface of the first conductive layer, and a third conductive layer on a contact region of the first gate structure. The second region is between the first region and the third region. The contact region is at a top of the first gate structure. A minimum distance between the second conductive layer and the third conductive layer is greater than zero.

Semiconductor structures are provided. A semiconductor structure includes a memory cell and a logic cell. The memory cell includes a latch circuit formed by two cross-coupled inverters, and a pass-gate transistor coupling an output of the latch circuit to a bit line. A first source/drain region of the pass-gate transistor is electrically connected to the bit line through a first contact over the first source/drain region and a first via over the first contact. A second source/drain region of a transistor of the logic cell is electrically connected to a local interconnect line through a second contact over the second source/drain region and a second via over the second contact. The local interconnect line and the bit line are formed in the same metal layer, and a top surface of the local interconnection line is lower than a top surface of the bit line.

An IC structure comprises a substrate, a first SRAM cell, and a second SRAM cell. The first SRAM cell is formed over the substrate and comprises a first N-type transistor. The second SRAM cell is formed over the substrate and comprises a second N-type transistor. A gate structure of first N-type transistor of the first SRAM cell has a different work function metal composition than a gate structure of the second N-type transistor of the second SRAM cell.