A semiconductor device includes a first fin that protrudes from a substrate and extends in a first direction, a second fin that protrudes from the substrate and extends in the first direction, the first fin and the second fin being spaced apart, a gate line including a dummy gate electrode and a gate electrode, the dummy gate electrode at least partially covering the first fin, the gate electrode at least partially covering the second fin, the dummy gate electrode including different materials from the gate electrode, the gate line covering the first fin and the second fin, the gate line extending in a second direction different from the first direction, and a gate dielectric layer between the gate electrode and the second fin.

A memory cell is disclosed. The memory cell includes a first transistor. The first transistor includes a first conduction channel collectively constituted by one or more first nanostructures spaced apart from one another along a vertical direction. The memory cell includes a second transistor electrically coupled to the first transistor in series. The second transistor includes a second conduction channel collectively constituted by one or more second nanostructures spaced apart from one another along the vertical direction. At least one of the one or more first nanostructures is applied with first stress by a first metal structure extending, along the vertical direction, into a first drain/source region of the first transistor.

Single gate and dual gate FinFET devices suitable for use in an SRAM memory array have respective fins, source regions, and drain regions that are formed from portions of a single, contiguous layer on the semiconductor substrate, so that STI is unnecessary. Pairs of FinFETs can be configured as dependent-gate devices wherein adjacent channels are controlled by a common gate, or as independent-gate devices wherein one channel is controlled by two gates. Metal interconnects coupling a plurality of the FinFET devices are made of a same material as the gate electrodes. Such structural and material commonalities help to reduce costs of manufacturing high-density memory arrays.

A band-shaped Si pillar having a mask material layer on the top portion thereof is formed on a P+ layer. SiGe layers having mask material layers on the top portions thereof are then formed in contact with the side surfaces of the band-shaped Si pillar and the surfaces of N+ layers and the P+ layer. Si layers having mask material layers on the top portions thereof are then formed in contact with the side surfaces of the SiGe layers and the surfaces of the N+ layers. The outer peripheries of the bottom portions of the Si layers are then removed using the mask material layers as a mask to form band-shaped Si pillars. The mask material layers and the SiGe layers are then removed. Si pillars separated in the Y direction are then formed in the band-shaped Si pillars.

Gate patterns are formed on a semiconductor layer and a conductive film is formed on the semiconductor layer so as to cover the gate patterns. By performing a polishing process to the conductive film and patterning the polished conductive film, pad layers are formed between the gate patterns via sidewall spacers.

A method includes providing a semiconductor substrate having a first region and a second region, epitaxially growing a semiconductor layer above the semiconductor substrate, patterning the semiconductor layer to form a first fin in the first region and a second fin in the second region, and depositing a dielectric material layer on sidewalls of the first and second fins. The method also includes performing an anneal process in driving dopants into the dielectric material layer, such that a dopant concentration in the dielectric material layer in the first region is higher than that in the second region, and performing an etching process to recess the dielectric material layer, thereby exposing the sidewalls of the first and second fins. A top surface of the recessed dielectric material layer in the first region is lower than that in the second region.

A read-port of a Static Random Access Memory (SRAM) cell includes a read-port pass-gate (R_PG) transistor and a read-port pull-down (R_PD) transistor. A write-port of the SRAM cell port includes at least a write-port pass-gate (W_PG) transistor, a write-port pull-down (W_PD) transistor, and a write-port pull-up (W_PU) transistor. The R_PG transistor, the R_PD transistor, the W_PG transistor, the W_PD transistor, and the W_PU transistor are gate-all-around (GAA) transistors. The R_PG transistor has a first channel width. The R_PD transistor has a second channel width. The W_PG transistor has a third channel width. The W_PD transistor has a fourth channel width. The W_PU transistor has a fifth channel width. The first channel width and the fourth channel width are each smaller than the second channel width. The third channel width is greater than the fifth channel width.

A dual-port memory cell includes first pull-up and pull-down transistors coupled at a first node between supply and reference voltage nodes, second pull-up and pull-down transistors coupled at a second node between the supply and reference voltage nodes, and first through fourth bit line landing pads in a metal layer. A first pass-gate transistor is coupled between the first bit line landing pad and the first node, a second pass-gate transistor is coupled between the second bit line landing pad and the second node, a third pass-gate transistor is coupled between the third bit line landing pad and the first node, and a fourth pass-gate transistor is coupled between the fourth bit line landing pad and the second node. The first node includes an interconnect between the first and second bit line landing pads, and the second node includes an interconnect between the third and fourth bit line landing pads.

Vertical transport field-effect transistors are formed on active regions wherein the active regions each include a wrap-around metal silicide contact on vertically extending side walls of the active region. Such wrap-around contacts form self-aligned and reliable strapping for SRAM bottom nFET and pFET source/drain regions. Buried contacts of SRAM cells may be used to strap the wrap-around metal silicide contacts with the gates of inverters thereof. Wrap-around metal silicide contacts provide additional contacts for logic FETs and reduce parasitic bottom source/drain resistance.

The present disclosure relates to a layout structure forming method of a sense amplifier and a layout structure of a sense amplifier. The method includes: providing a first active region layout structure layer, the first metal contact pattern layer includes a first metal contact pattern and a second metal contact pattern that are located on two opposite sides of the first pattern region; the first conductive wire pattern layer includes a first conductive wire pattern covering the first metal contact pattern and the second metal contact pattern; and the first connection hole pattern layer includes a plurality of connection hole designs, and the connection hole designs are connected to form a connection structure connected to the first metal contact pattern layer.