The present disclosure allows for reducing parasitic capacitance of a bit line, and a drop in access performance in an SRAM cell including fin-type transistors. The SRAM cell is defined by transistors each of which has a fin structure and by a local metal interconnection layer. Bit lines are formed on the local metal interconnection layer, and diffusion layer contacts corresponding to bit line nodes are connected through vias to the bit lines.

Embodiments of 3D memory devices with a static random-access memory (SRAM) and fabrication methods thereof are disclosed herein. In certain embodiments, the 3D memory device includes a first semiconductor structure and a second semiconductor structure. The first semiconductor structure includes an array of SRAM cells and a first bonding layer, and the second semiconductor structure includes an array of 3D NAND memory strings and a second bonding layer. The first semiconductor structure is attached with the second semiconductor structure through the first bonding layer and the second bonding layer. The array of 3D NAND memory strings and the array of SRAM cells are coupled through a plurality of bonding contacts in the first bonding layer and the second bonding layer and are arranged at opposite sides of the plurality of bonding contacts.

A semiconductor structure includes an array of two-port (TP) SRAM cells, each of which includes a write port and a read port. The write port includes two write pass gate (W_PG) transistors, two write pull-down (W_PD) transistors, and two write pull-up (W_PU) transistors. The array of TP SRAM cells includes first and second TP SRAM cells whose write ports abuts each other. Two W_PG transistors of the first and second TP SRAM cells share a common gate electrode. Source/drain electrodes of two W_PD transistors of the first and second TP SRAM cells share a common contact. The first TP SRAM cell includes a Vss conductor connected to the common contact. The second TP SRAM cell includes a write word line (W_WL) landing pad connected to the common gate electrode. The Vss conductor and the W_WL landing pad are located at a first metal layer.

Based on a basic idea to effectively utilize a space created in a third wiring layer (M3) by a zero-th wiring layer (M0) which can exist by miniaturization of a FINFET, an auxiliary line AL is arranged in the space created in the third wiring layer, and this auxiliary line AL and a word line WL are electrically connected to each other. Thus, a measure (device) based on such new knowledge that rising time of a word line voltage is largely affected by a wiring resistance of the word line is achieved, a high-speed operation in an SRAM using the FINFET is achieved.

Circuit structures, such as inverters and static random access memories, and fabrication methods thereof are presented. The circuit structures include, for instance: a first transistor, the first transistor having a first channel region disposed above an isolation region; and a second transistor, the second transistor having a second channel region, the second channel region being laterally adjacent to the first channel region of the first transistor and vertically spaced apart therefrom by the isolation region thereof. In one embodiment, the first channel region and the isolation region of the first transistor are disposed above a substrate, and the substrate includes the second channel region of the second transistor.

A semiconductor device is provided, including: a substrate having a first area and a second area; several first gate structures formed at the first area, and at least one of the first gate structures including a first hardmask on a first gate, and the first gate structure having a first gate length; several second gate structures formed at the second area, and at least one of the second gate structures including a second hardmask on a second gate, and the second gate structure having a second gate length. The first gate length is smaller than the second gate length, and the first hardmask contains at least a portion of nitrogen (N.sub.2)-based silicon nitride (SiN) which is free of OH concentration.

A semiconductor device includes first and second semiconductor fins extending from a substrate and a source/drain region epitaxially grown in recesses of the first and second semiconductor fins. A top surface of the source/drain region is higher than a surface level with top surfaces of the first and second semiconductor fins. The source/drain region includes a plurality of buffer layers. Respective layers of the plurality of buffer layers are embedded between respective layers of the source/drain region. Each of the plurality of buffer layers may have an average thickness in a range of about 2 Å to about 30 Å.

A semiconductor device includes a substrate with an NMOSFET region and a PMOSFET region, a first active pattern on the NMOSFET region, a second active pattern on the PMOSFET region, a dummy pattern between the NMOSFET and PMOSFET regions, and device isolation patterns on the substrate that fill trenches between the first active pattern, the second active pattern, and the dummy pattern. Upper portions of the first and second active patterns have a fin-shaped structure protruding between the device isolation patterns. The upper portions of the first and second active patterns contain semiconductor materials, respectively, that are different from each other, and an upper portion of the dummy pattern contains an insulating material.

A device includes a master latch, a slave latch and a retention latch coupled to each other. The retention latch includes first and second active areas, first and second gate structures. The first and second active areas extend in a first direction. The first gate structure extends in a second direction, the first gate structure including first and second portions that are separated from each other. The first portion is arranged over the first active area, and the second portion is arranged over the second active area. The second gate structure extends in the second direction, and is arranged over the first active area. The second gate structure is separated from the second active area and the first gate structure in a layout view. An end portion of the second active area is between the first gate structure and the second gate structure.

An integrated circuit includes: a cell array including a plurality of memory cells in a plurality of first columns and including a plurality of word line assist cells in at least one second column; a plurality of word lines respectively extending on a plurality of first rows of the cell array and connected to the plurality of memory cells and the plurality of word line assist cells; and a row driver configured to drive the plurality of word lines.