When VC inspection for a TEG is performed, it is easily detected whether any failure of a contact plug occurs or not by increasing an emission intensity of a contact plug, so that reliability of a semiconductor device is improved. An element structure of an SRAM is formed on an SOI substrate in a chip region. Also, in a TEG region, an element structure of an SRAM in which a contact plug is connected to a semiconductor substrate is formed on the semiconductor substrate exposed from an SOI layer and a BOX film as a TEG used for the VC inspection.

A method for manufacturing a semiconductor device includes the steps of: determining a first design dimension of a gate electrode of a selection MISFET, a second design dimension of a sidewall insulating film, and initial setting conditions for ion implantation for a high-concentration semiconductor region; forming the gate electrode; measuring a first processed dimension of the gate electrode; implanting ions to form a low-concentration semiconductor region at each end of the gate electrode; forming the sidewall insulating film over a sidewall of the gate electrode; measuring a second processed dimension of the sidewall insulating film; and implanting ions to form a high-concentration semiconductor region. In the former implantation step, execution conditions to the initial setting conditions are reset according to a deviation of the first processed dimension from the first design dimension and a deviation of the second processed dimension from the second design dimension, and the step is executed.

A semiconductor device includes a first transistor, a second transistor and a third transistor provided on a substrate, the first to third transistors respectively including source and drain regions spaced apart from each other, a gate structure extending in a first direction on the substrate and interposed between the source and drain regions, and a channel region connecting the source and drain regions to each other. A channel region of the second transistor and a channel region of the third transistor respectively include a plurality of channel portions, the plurality of channel portions spaced apart from each other in a second direction, perpendicular to an upper surface of the substrate, and connected to the source and drain regions, respectively. A width of a channel portion of the third transistor in the first direction is greater than a width of a channel portion of the second transistor in the first direction.

A method of fabricating a memory includes forming a first portion of a first line in a first metal layer, forming a first portion of a second line in the first metal layer, forming a second portion of the first line in a second metal layer, and forming a second portion of the second line in a third metal layer. The first line is over a plurality of memory cells. The second line is over the plurality of memory cells, the first line is electrically isolated from the second line, and the first line and the second line extend in a same direction. The second metal layer is over the first metal layer. The third metal layer is over the second metal layer and the third metal layer is electrically isolated from the first line.

A chip includes a semiconductor substrate, and a first N-type Metal Oxide Semiconductor Field Effect Transistor (NMOSFET) at a surface of the semiconductor substrate. The first NMOSFET includes a gate stack over the semiconductor substrate, a source/drain region adjacent to the gate stack, and a dislocation plane having a portion in the source/drain region. The chip further includes a second NMOSFET at the surface of the semiconductor substrate, wherein the second NMOSFET is free from dislocation planes.

An electronic circuit includes a Ternary Content-Addressable Memory (TCAM) array. The TCAM array includes a plurality of TCAM cells that include a first signal line. The first signal line is located in a first metal layer. The TCAM array includes a connection structure that includes a first metal landing pad. The first metal landing pad is located in a second metal layer different from the first metal layer. The electronic circuit includes a periphery circuit located near the TCAM array. The periphery circuit includes a first metal line located in the first metal layer. The first metal line extends in a direction parallel to the first signal line but is misaligned with the first signal line in a planar view. The first metal landing pad is electrically coupled to both the first signal line and the first metal line.

Static random access memory (SRAM) bit cells employing asymmetric width read and write word lines (WWL) for reduced memory write latency and improved memory write access performance, and related fabrication methods are disclosed. In exemplary aspects, the SRAM bit cell employs an increased width write word line based on a circuit cell layout area savings achieved by employing a reduced width read word line. Increasing the width of the write word line can reduce the resistance of the write word line and decrease memory write latency to the SRAM bit cell as a result. In certain exemplary aspects, the metal line pitch and minimum distance between metal lines of the SRAM bit cell can be maintained for maintaining fabrication compatibility with existing fabrication processes with decreasing the resistance of the write word line of the SRAM bit cell.

Devices and methods of fabricating integrated circuit devices with reduced cell height are provided. One method includes, for instance: obtaining an intermediate semiconductor device having a substrate including a logic area and an SRAM area, a fin material layer, and a hardmask layer; depositing a mandrel over the logic area; depositing a sacrificial spacer layer; etching the sacrificial spacer layer to define a sacrificial set of vertical spacers; etching the hardmask layer; leaving a set of vertical hardmask spacers; depositing a first spacer layer; etching the first spacer layer to define a first set of vertical spacers over the logic area; depositing an SOH layer; etching an opening in the SOH layer over the SRAM area; depositing a second spacer layer; and etching the second spacer layer to define a second set of spacers over the SRAM area.

A 3D semiconductor device including: a first level including a first single-crystal layer, a plurality of first transistors, a first metal layer (includes interconnection of first transistors), and a second metal layer, where first transistors' interconnection includes forming logic gates; a plurality of second transistors disposed atop, at least in part, of logic gates; a plurality of third transistors disposed atop, at least in part, of the second transistors; a third metal layer disposed above, at least in part, the third transistors; a global grid to distribute power and overlaying, at least in part, the third metal layer; a local grid to distribute power to the logic gates, the local grid is disposed below, at least in part, the second transistors, where the second transistors are aligned to the first transistors with less than 40 nm misalignment, where at least one of the second transistors includes a metal gate.

An integrated circuit device includes an active area extending in a first direction on a substrate and a gate line extending in a second direction intersecting with the first direction to intersect with the active area. The gate line comprises a first sidewall and a second sidewall opposite to each other. The first sidewall has a convex shape. The second sidewall has a concave shape.