To provide a semiconductor device having a thin-film BOX-SOI structure and capable of realizing a high-speed operation of a logic circuit and a stable operation of a memory circuit. A semiconductor device according to the present invention includes a semiconductor support substrate, an insulation layer having a thickness of at mast 10 nm, and a semiconductor layer. In an upper surface of the semiconductor layer, a first field-effect transistor including a first gate electrode and constituting a logic circuit is formed. Further, in the upper surface of the semiconductor layer, a second field-effect transistor including a second gate electrode and constituting a memory circuit is formed. At least three well regions having different conductivity types are formed in the semiconductor support substrate. In the presence of the well regions, a region of the semiconductor support substrate below the first gate electrode and a region of the semiconductor support substrate below the second gate electrode are electrically separated from each other.

A method for processing a 3D integrated circuit, the method including: providing a first level including a first wafer, the first wafer including a first crystalline substrate, a plurality of first transistors, and first copper interconnecting layers, where the first copper interconnecting layers at least interconnect the plurality of first transistors; processing a second level including a second wafer, the second wafer including a second crystalline substrate, a plurality of second transistors, and second copper interconnecting layers, where the second copper interconnecting layers at least interconnect the plurality of second transistors; then forming a bonded structure by bonding the second level to the first level, where the bonding includes metal to metal bonding, where the bonding includes oxide to oxide bonding; and then performing a lithography process to define dice lines for the bonded structure; and etching the dice lines.

A method of designing a circuit is provided. The method includes: providing a circuit; selecting a first NMOS fin field-effect transistor (FinFET) in the circuit; and replacing the first NMOS FinFET having a first fin number with a second NMOS FinFET having a second fin number and a third NMOS FinFET having a third fin number, wherein the sum of the second fin number and the third fin number is equal to the first fin number.

Memory devices are provided. In an embodiment, a memory device includes a static random access memory (SRAM) array. The SRAM array includes a static random access memory (SRAM) array. The SRAM array includes a first subarray including a plurality of first SRAM cells and a second subarray including a plurality of second SRAM cells. Each n-type transistor in the plurality of first SRAM cells includes a first work function stack and each n-type transistor in the plurality of second SRAM cells includes a second work function stack different from the first work function stack.

A semiconductor device according to the present disclosure includes first gate-all-around (GAA) devices in a first device area and second GAA devices in a second device area. Each of the first GAA devices includes a first vertical stack of channel members, a first gate structure over and around the first vertical stack of channel members, and a plurality of inner spacer features. Each of the second GAA devices includes a second vertical stack of channel members and a second gate structure over and around the second vertical stack of channel members. Two adjacent channel members of the first vertical stack of channel members are separated by a portion of the first gate structure and at least one of the plurality of inner spacer features. Two adjacent channel members of the second vertical stack of channel members are separated only by a portion of the second gate structure.

There are provided a semiconductor memory device and a manufacturing method thereof. The semiconductor memory device includes: a first etch stop layer; a source layer on the first etch stop layer; a second etch stop layer on the source layer; a stack structure on the second etch stop layer; and a channel structure penetrating the first and second etch stop layers, the source layer, and the stack structure, the channel structure being electrically connected to the source layer. A material of each of the first and second etch stop layers has an etch selectivity with respect to a material of the source layer.

Embodiments of 3D memory devices with a static random-access memory (SRAM) and fabrication methods thereof are disclosed herein. In one example, the method for operating a 3D memory device having an input/output circuit, an array of SRAM cells, and an array of 3D NAND memory strings in a same chip. The method may include transferring data through the input/output circuit to the array of SRAM cells, storing the data in the array of SRAM cells, and programming the data into the array of 3D NAND memory strings from the array of SRAM cells.

Embodiments of semiconductor devices and fabrication methods thereof are disclosed. In an example, a semiconductor device includes a first semiconductor structure including a processor and a first bonding layer including a plurality of first bonding contacts. The semiconductor device also includes a second semiconductor structure including an array of static random-access memory (SRAM) cells and a second bonding layer including a plurality of second bonding contacts. The semiconductor device further includes a bonding interface between the first bonding layer and the second bonding layer. The first bonding contacts are in contact with the second bonding contacts at the bonding interface.

A three-dimensional (3D) integrated circuit (IC) includes a substrate having a substrate surface, a power rail provided in the substrate, and a first tier of semiconductor devices provided in the substrate and positioned over the power rail along a thickness direction of the substrate. A wiring tier is provided in the substrate, and a second tier of semiconductor devices is provided in the substrate and positioned over the wiring tier along the thickness direction. The second tier of semiconductor devices is stacked on the first tier of semiconductor devices in the thickness direction such that the wiring tier is interposed between the first and second tiers of semiconductor devices. A first vertical interconnect structure extends downward from the wiring tier to the first tier of semiconductor devices to electrically connect the wiring tier to a device within the first tier of semiconductor devices. A second vertical interconnect structure extends upward from the wiring tier to the second tier of semiconductor devices to electrically connect the wiring tier to a device within the second tier of semiconductor devices.

Disclosed is a semiconductor memory device comprising a plurality of memory cells each including an access transistor, a pull-up transistor, and a pull-down transistor on a substrate, a first line layer on the memory cells and including a first lower landing pad and a second lower landing pad, a second line layer on the first line layer and including a ground line having an opening and an upper landing pad in the opening, and a third line layer including a word line on the second line layer. The ground line is electrically connected through the first lower landing pad to a terminal of the pull-down transistor. The word line is electrically connected through the upper landing pad and the second lower landing pad to a terminal of the access transistor.