In a semiconductor device, a first stack is positioned over substrate and includes a first pair of transistors and a second pair of transistors stacked over the substrate. A second stack is positioned over the substrate and adjacent to the first stack. The second stack includes a third pair of transistors and a fourth pair of transistors stacked over the substrate. A first capacitor is stacked with the first and second stacks. A second capacitor is positioned adjacent to the first capacitor and stacked with the first and second stacks. A first group of the transistors in the first and second stacks is coupled to each other to form a static random-access memory cell. A second group of the transistors in the first and second stacks is coupled to the first and second capacitors to form a first dynamic random-access memory (DRAM) cell and a second DRAM cell.

A semiconductor memory device includes a stack disposed over a first substrate; an etch barrier including a plurality of dummy channels which pass through the stack and surround a coupling region; and a plurality of channels passing through the stack in a cell region outside the coupling region. The stack has a structure in which first dielectric layers and second dielectric layers are alternately stacked, inside the coupling region, and has a structure in which the first dielectric layers and electrode layers are alternately stacked, outside the coupling region.

A method of designing a circuit is provided. The method includes: providing a circuit; selecting a first NMOS fin field-effect transistor (FinFET) in the circuit; and replacing the first NMOS FinFET having a first fin number with a second NMOS FinFET having a second fin number and a third NMOS FinFET having a third fin number, wherein the sum of the second fin number and the third fin number is equal to the first fin number.

A semiconductor chip is provided. The semiconductor chip includes a SRAM cell, a logic cell, a signal line and a ground line. The SRAM cell includes a storage transmission gate, a read transmission gate and a latch circuit. The latch circuit is serially connected between the storage and read transmission gates, and includes a first inverter, a second inverter and a transmission gate connected to an output of the first inverter, an input of the second inverter and an output of the storage transmission gate. The logic cell disposed aside the SRAM cell is connected with the SRAM cell by first and second active structures. The signal and ground lines extend at opposite sides of the SRAM and logic cells, and are substantially parallel with the first and second active structures. The SRAM and logic cells are disposed between and electrically connected to the signal and ground lines.

Methods, systems, and devices for thin film transistor random access memory are described. A memory device may include memory cells each having one or more transistors formed above a substrate. For example, a memory cell may include a transistor having a channel portion formed by one or more pillars or other structures formed above a substrate, and a gate portion including a conductor formed above the substrate and configured to activate the channel portion based at least in part on a voltage of the gate portion. A memory cell may include a set of two or more such transistors to support latching circuitry of the memory cell, or other circuitry configured to store a logic state, which may or may not be used in combination with one or more transistors formed at least in part from one or more portions of a substrate.

Various embodiments of the present application are directed towards a memory device including a memory cell. The memory cell includes a plurality of semiconductor devices disposed on a substrate. A lower inter-metal dielectric (IMD) structure overlies the semiconductor devices. A plurality of conductive vias and a plurality of conductive wires are disposed within the IMD structure and are electrically coupled to the semiconductor devices. A data backup unit overlies the plurality of conductive vias and wires. The data backup unit includes a first source/drain structure, a second source/drain structure, a channel layer, a first memory gate structure, and a second memory gate structure. The first and second memory gate structures include an upper gate electrode over a ferroelectric layer. The first and second source/drain structures are directly electrically coupled to the semiconductor devices by way of the conductive vias and wires.

Various implementations of backside and topside routing of bitlines and wordlines in memory arrays are disclosed. Bitlines in backside and topside metal layers may be alternated between adjacent bit cells in a memory array. Alternating the location of the bitlines between bit cells in the memory array may reduce bitline capacitance in a memory array. Placing wordlines in backside metal layers may allow dual wordlines to be implemented across a span of bit cells in a memory array. The dual wordlines may be alternately connected to adjacent bit cells, thereby allowing selective toggling of bit cells based on the wordline transmitting a control signal.

A cell layout that may be implemented in FinFET devices or other FET devices is disclosed. The cell layout includes a control signal route that passes from a first device into backside layers and then underneath a second device. The control signal route then routes back to topside metal layers through inactive transistors that are implemented as via structures on the other side of the second device. Connection to the gate of the second device may then be completed through the topside metal layers. The disclosed control signal route provides a low resistance path that reduces RC delay in the devices in the cell layout.

Techniques herein include methods of forming higher density circuits by combining multiple substrates via stacking and bonding of individual substrates. High voltage and low voltage devices along with 3D NAND devises are fabricated on a first wafer, and high voltage and low voltage devices and/or memory are then fabricated on a second wafer and/or third wafer.

Embodiments of semiconductor devices and fabrication methods thereof are disclosed. In an example, a semiconductor device includes NAND memory cells and a first bonding layer including first bonding contacts. The semiconductor device also includes a second semiconductor structure including DRAM cells and a second bonding layer including second bonding contacts. The semiconductor device also includes a third semiconductor structure including a processor, SRAM cells, and a third bonding layer including third bonding contacts. The semiconductor device further includes a first bonding interface between the first and third bonding layers, and a second bonding interface between the second and third bonding layers. The first bonding contacts are in contact with a first set of the third bonding contacts at the first bonding interface. The second bonding contacts are in contact with a second set of the third bonding contacts at the second bonding interface. The first and second bonding interfaces are in a same plane.