A semiconductor structure includes a substrate and first and second SRAM cells. The first SRAM cell includes first and second pull-up transistors, first and second pull-down transistors, and first and second pass-gate transistors. The first and the second pass-gate transistors have a first channel width. The first and the second pull-down transistors have a second channel width. A ratio of the second channel width to the first channel width is in a range of 1.05 to 1.5. The second SRAM cell includes third and fourth pull-up transistors, third and fourth pull-down transistors, and third and fourth pass-gate transistors. The third and the fourth pass-gate transistors have a third channel width. The third and the fourth pull-down transistors have a fourth channel width. The third and the fourth channel widths are substantially same. The fourth channel width is larger than the second channel width. The transistors are GAA transistors.

An IC chip includes a logic circuit cells array and a static random access memory (SRAM) cells array. The logic circuit cells array includes a plurality of logic circuit cells abutted to one another in a first direction. The logic circuit cells array includes one or more continuous first fin lines that each extends across at least three of the abutted logic circuit cells in the first direction. The static random access memory (SRAM) cells array includes a plurality of SRAM cells abutted to one another in the first direction. The SRAM cells array includes discontinuous second fin lines.

A semiconductor memory device includes an array of memory cells arranged in a plurality of rows and columns, with each memory cell including a plurality of bit cell transistors. The semiconductor memory device further includes a plurality of write assist circuits, including one or more write assist circuits within each column of the array of memory cells, each write assist circuit configured to provide a core voltage to memory cells within the same column and to reduce the core voltage during a write operation. The array of memory cells and the plurality of write assist circuits have a common semiconductor layout.

A semiconductor structure includes: a substrate; a gate structure on the substrate; and an interconnect structure including a first interconnect sub-structure and a second interconnect sub-structure, where the second interconnect sub-structure protrudes from the first interconnect sub-structure. The first interconnect sub-structure is connected with the substrate, and the second interconnect sub-structure is connected with a top of the gate structure.

A semiconductor device includes a first regulator for generating a first power supply potential, a second regulator for generating a second power supply potential lower than the first power supply potential, and a static random access memory (SRAM) having a normal operation mode and a resume standby mode. The SRAM includes power supply switching circuits receiving a first power supply potential and a second power supply potential, and a memory array including a plurality of memory cells. When the SRAM is in the normal operation mode, the power switch circuit is controlled so that the first power supply potential is supplied from the power switch circuit to the memory array, and when SRAM is in the resume standby mode, the second power supply potential is supplied from the power switch circuit to the memory array.

Zero expanded functional gate structures are formed by utilizing a dipole material spacer as a means to prevent expanded void formation during a replacement metal gate process. Notably, the dipole material spacer prevents expanded void formation into the dielectric spacer thus preventing the functional gate structures from being in direct physical contact with the source/drain regions. Improvement in yield loss and reliability is thus provided utilizing a dipole material spacer during a replacement metal gate process.

A semiconductor device according to the present disclosure includes a gate-all-around (GAA) transistor in a first device area and a fin-type field effect transistor (FinFET) in a second device area. The GAA transistor includes a plurality of vertically stacked channel members and a first gate structure over and around the plurality of vertically stacked channel members. The FinFET includes a fin-shaped channel member and a second gate structure over the fin-shaped channel member. The fin-shaped channel member includes semiconductor layers interleaved by sacrificial layers.

A method includes etching a silicon layer in a wafer to form a first trench in a first device region and a second trench in a second device region, performing a pre-clean process on the silicon layer, performing a baking process on the wafer, and performing an epitaxy process to form a first silicon germanium region and a second silicon germanium region in the first trench and the second trench, respectively. The first silicon germanium region and the second silicon germanium region have a loading in a range between about 5 nm and about 30 nm.

A method for producing a 3D semiconductor device including: providing a first level including a first single crystal layer; forming peripheral circuitry in and/or on the first level, and includes first single crystal transistors; forming a first metal layer on top of the first level; forming a second metal layer on top of the first metal layer; forming second level disposed on top of the second metal layer; performing a first lithography step; forming a third level on top of the second level; performing a second lithography step; processing steps to form first memory cells within the second level and second memory cells within the third level, where the plurality of first memory cells include at least one second transistor, and the plurality of second memory cells include at least one third transistor; and deposit a gate electrode for second and third transistors simultaneously.

A semiconductor device includes a substrate having an input/output (I/O) region, an one time programmable (OTP) capacitor region, and a core region, a first metal gate disposed on the I/O region, a second metal gate disposed on the core region, and a third metal gate disposed on the OTP capacitor region. Preferably, the first metal gate includes a first high-k dielectric layer, the second metal gate includes a second high-k dielectric layer, and the first high-k dielectric layer and the second high-k dielectric layer include an I-shape.