An integrated circuit device includes a FinFET disposed over a doped region of a first type dopant, wherein the FinFET includes a first fin structure and first source/drain (S/D) features, the first fin structure having a first width; and a fin-based well strap disposed over the doped region of the first type dopant, wherein the fin-based well strap includes a second fin structure and second S/D features, the second fin structure having a second width that is larger than the first width, wherein the fin-based well strap connects the doped region to a voltage.

A connecting structure includes a substrate, a first conductive feature, a second conductive feature, a third conductive feature over the first conductive feature, and a fourth conductive feature over the second conductive feature. The substrate includes a first region and a second region. The first conductive feature is disposed in the first region and has a first width. The second conductive feature is disposed in the second region and has a second width greater than the first width of the first conductive feature. The third conductive feature includes a first anchor portion surrounded by the first conductive feature. The fourth conductive feature includes a second anchor portion surrounded by the second conductive feature. A depth difference ratio between a depth of the first anchor portion and a depth of the second anchor portion is less than approximately 10%.

An integration system includes a first monolithic die and a second monolithic die. The first monolithic die has a processing unit circuit formed therein; and the second monolithic die has a plurality of SRAM arrays formed therein. Wherein the second monolithic die comprises at least 2G Bytes; and the first monolithic die is electrically connected to the second monolithic die.

Memory devices are provided. In an embodiment, a memory device includes a static random access memory (SRAM) array. The SRAM array includes a static random access memory (SRAM) array. The SRAM array includes a first subarray including a plurality of first SRAM cells and a second subarray including a plurality of second SRAM cells. Each n-type transistor in the plurality of first SRAM cells includes a first work function stack and each n-type transistor in the plurality of second SRAM cells includes a second work function stack different from the first work function stack.

The current disclosure is directed to a SRAM bit cell having a reduced coupling capacitance. In a vertical direction, a wordline “WL” and a bitline “BL” of the SRAM cell are stacked further away from one another to reduce the coupling capacitance between the WL and the BL. In an embodiment, the WL is vertically spaced apart from the BL with one or more metallization level that none of the WL or the BL is formed from. Connection island structures or jumper structures are provided to connect the upper one of the WL or the BL to the transistors of the SRAM cell.

A read-port of a Static Random Access Memory (SRAM) cell includes a read-port pass-gate (R_PG) transistor and a read-port pull-down (R_PD) transistor. A write-port of the SRAM cell port includes at least a write-port pass-gate (W_PG) transistor, a write-port pull-down (W_PD) transistor, and a write-port pull-up (W_PU) transistor. The R_PG transistor, the R_PD transistor, the W_PG transistor, the W_PD transistor, and the W_PU transistor are gate-all-around (GAA) transistors. The R_PG transistor has a first channel width. The R_PD transistor has a second channel width. The W_PG transistor has a third channel width. The W_PD transistor has a fourth channel width. The W_PU transistor has a fifth channel width. The first channel width and the fourth channel width are each smaller than the second channel width. The third channel width is greater than the fifth channel width.

In some implementations, a method of fabricating an integrated circuit includes obtaining first data for a first chip containing a first version of the integrated circuit, determining that a transistor should be coupled with another transistor, selecting one or more masks for coupling the transistor with the other transistor to adjust the threshold voltage of the transistor, obtaining second data for a second chip containing a second version of the integrated circuit, determining that the second version of the integrated circuit meets one or more requirements, and preparing a final integrated circuit design for production based on the second version of the integrated circuit.

A semiconductor device includes an active area extending in a first direction, a first transistor including a first gate electrode and first source and drain areas disposed on the active area, the first source and drain areas being disposed at opposite sides of the first gate electrode, a second transistor including a second gate electrode and second source and drain areas disposed on the active area, the second source and drain areas being disposed at opposite sides of the second gate electrode, and a third transistor including a third gate electrode and third source and drain areas disposed on the active area, the third source and drain areas being disposed at opposite sides of the third gate electrode, and the first gate electrode, the second gate electrode, and the third gate electrode extending in a second direction different from the first direction. The second transistor is configured to turn on and off, based on an operation mode of the semiconductor device.

A storage device includes a first semiconductor structure having a first cell area, with memory cells disposed on a first semiconductor substrate, and a first metal pad disposed above the first cell area. A second semiconductor structure has a peripheral circuit area on a second semiconductor substrate and on which peripheral circuits are disposed, a second cell area including a plurality of second memory cells, and a second metal pad bonded to the first metal pad. A third semiconductor structure includes a memory controller disposed on a third semiconductor substrate and connected to a third metal pad through a connection via penetrating through the third semiconductor substrate. A connection structure penetrates through the second semiconductor substrate and connects the memory controller to the second semiconductor structure. The memory controller controls the first and second cell areas based on a signal applied from a host through the third metal pad.

An IC is provided. The IC includes a first P-type FinFET and a second P-type FinFET. The first P-type FinFET includes a silicon germanium channel region. The second P-type FinFET includes a Si channel region. First source/drain regions of the first P-type FinFET are formed on a discontinuous semiconductor fin, and second source/drain regions of the second P-type FinFET are formed on a continuous semiconductor fin. A first depth of the first source/drain regions is different from a second depth of the second source/drain regions.