A method of manufacturing a semiconductor device includes: forming a lower structure that includes a substrate and conductive lines on the substrate, within a chip region and an edge region of the lower structure; forming data storage structures on the chip region of the lower structure; forming dummy structures on the edge region of the lower structure; forming an interlayer insulating layer covering the data storage structures and the dummy structures on the lower structure, the interlayer insulating layer including high step portions and low step portions, an upper end of the low step portions being lower than an upper end of the high step portions; and planarizing the interlayer insulating layer.

A semiconductor structure includes an active area in a substrate, a device isolation region surrounding the active area, first and second bit line structures on the substrate, a conductive diffusion region in the active area between the first and the second bit line structures, and a contact hole between the first and the second bit line structures. The contact hole partially exposes the conductive diffusion region. A buried plug layer is disposed in the contact hole and in direct contact with the conductive diffusion region. A storage node contact layer is disposed on the buried plug layer within the contact hole. The storage node contact layer has a downwardly protruding portion surrounded by the buried plug layer. The buried plug layer has a U-shaped cross-sectional profile.

A substrate structure of the memory, and a method for preparing the substrate structure of the memory are provided. The method includes: providing a substrate; forming a first mask layer on the substrate, the first mask layer including a plurality of strip patterns extending in a direction and spaced apart from each other; forming a first dielectric layer covering the first mask layer; forming a plurality of sacrificial portions spaced apart from each other in the first dielectric layer and covering a portion of the plurality of strip patterns; filling gaps between the sacrificial portions with a second dielectric material; forming a second mask layer by removing the sacrificial portions while retaining the second dielectric material in the gaps; and performing layer-by-layer etching into the substrate to form a plurality of active areas arranged in an array.

A semiconductor structure and a manufacturing method thereof are provided. The method includes: providing a substrate; forming, on the substrate, a first mask layer having a plurality of strip-shaped first patterns arranged in parallel; forming, on the first mask layer, a second mask layer having a plurality of strip-shaped second patterns arranged in parallel; forming, on the second mask layer, a third mask layer having a plurality of strip-shaped third patterns arranged in parallel, the second patterns overlap with the third patterns, and the second patterns and the third patterns are configured to sever the first patterns at predetermined positions; and performing layer-by-layer etching, using the first mask layer, the second mask layer, and the third mask layer as masks to transfer the first patterns, the second patterns, and the third patterns to the substrate to form an array of discrete active areas.

Most semiconductor devices manufactured today, have uniform dopant concentration, either in the lateral or vertical device active (and isolation) regions. By grading the dopant concentration, the performance in various semiconductor devices can be significantly improved. Performance improvements can be obtained in application specific areas like increase in frequency of operation for digital logic, various power MOSFET and IGBT ICs, improvement in refresh time for DRAMs, decrease in programming time for nonvolatile memory, better visual quality including pixel resolution and color sensitivity for imaging ICs, better sensitivity for varactors in tunable filters, higher drive capabilities for iFETs, and a host of other applications.

An apparatus is described. The apparatus includes a compute-in-memory (CIM) circuit for implementing a neural network disposed on a semiconductor chip. The CIM circuit includes a mathematical computation circuit coupled to a memory array. The memory array includes an embedded dynamic random access memory (eDRAM) memory array. Another apparatus is described. The apparatus includes a compute-in-memory (CIM) circuit for implementing a neural network disposed on a semiconductor chip. The CIM circuit includes a mathematical computation circuit coupled to a memory array. The mathematical computation circuit includes a switched capacitor circuit. The switched capacitor circuit includes a back-end-of-line (BEOL) capacitor coupled to a thin film transistor within the metal/dielectric layers of the semiconductor chip. Another apparatus is described. The apparatus includes a compute-in-memory (CIM) circuit for implementing a neural network disposed on a semiconductor chip. The CIM circuit includes a mathematical computation circuit coupled to a memory array. The mathematical computation circuit includes an accumulation circuit. The accumulation circuit includes a ferroelectric BEOL capacitor to store a value to be accumulated with other values stored by other ferroelectric BEOL capacitors.

A method for example manufacturing a semiconductor device, which includes: forming a hole in a region of an insulating film laminated on a substrate; embedding a first conductive material in the hole to a position lower than a height of a sidewall of the hole; further embedding a second conductive material through a selective growth in the hole in which the first conductive material has been embedded; and etching the second conductive material to form a contact pad at a position above the hole.

Integrated circuit devices having multiple level arrays of thyristor memory cells are created using a stack of ONO layers through which NPNPNPN layered silicon pillars are epitaxially grown in-situ. Intermediate conducting lines formed in place of the removed nitride layer of the ONO stack contact the middle P-layer of silicon pillars. The silicon pillars form two arrays of thyristor memory cells, one stacked upon the other, having the intermediate conducting lines as common connections to both arrays. The stacked arrays can also be provided with assist-gates.

A semiconductor device includes a gate structure on a substrate, in which the gate structure includes a silicon layer on the substrate, a titanium nitride (TiN) layer on the silicon layer, a titanium (Ti) layer between the TiN layer and the silicon layer, a metal silicide between the Ti layer and the silicon layer, a titanium silicon nitride (TiSiN) layer on the TiN layer, and a conductive layer on the TiSiN layer.

Some embodiments include apparatuses and methods of forming the apparatuses. One of the apparatuses includes multiple levels of two-transistor (2T) memory cells vertically arranged above a substrate. Each 2T memory cell includes a charge storage transistor having a gate, a write transistor having a gate, a vertically extending access line, and a single bit line pair. The source or drain region of the write transistor is directly coupled to a charge storage structure of the charge storage transistor. The vertically extending access line is coupled to gates of both the charge storage transistor and the write transistor of 2T memory cells in multiple respective levels of the multiple vertically arranged levels. The vertically extending access line and the single bit line pair are used for both write operations and read operations of each of the 2T memory cells to which they are coupled.