Apparatuses and methods to provide a patterned substrate are described. A plurality of patterned and spaced first lines and carbon material lines and formed on the substrate surface by selectively depositing and etching films extending in a first direction and films extending in a second direction that crosses the first direction to pattern the underlying structures.

Some embodiments include apparatuses and methods of forming the apparatuses. One of the apparatuses includes a memory cell and first, second, and third data lines located over a substrate. The memory cell includes a first transistor and a second transistor. The first transistor includes a charge storage structure located on a first level of the apparatus, and a first channel region electrically separated from the charge storage structure. The second transistor includes a second channel region located on a second level of the apparatus and electrically coupled to the charge storage structure. The first and second data lines are located on a third level of the apparatus and electrically coupled to the first channel region. The first level is between the substrate and the third level. The third data line is electrically coupled to the second channel region and electrically separated from the first channel region.

With the disclosed systems and methods for DRAM and 3D NAND inspection, an image of the wafer is received based on the output for an inspection tool. Geometric measurements of a design of a plurality of memory devices on the wafer are received. A care area with higher inspection sensitivity is determined based on the geometric measurements.

A semiconductor memory device includes a memory cell array of a three-dimensional structure including a plurality of memory cells repeatedly arranged in a first horizontal direction and a second horizontal direction that are parallel with a main surface of a substrate and cross each other on the substrate and in a vertical direction perpendicular to the main surface, wherein each of the plurality of memory cells includes three transistors. A method of manufacturing a semiconductor memory device includes forming simultaneously a plurality of memory cells arranged in a row in a vertical direction on a substrate, wherein each of the plurality of memory cells includes three transistors.

Disclosed is a semiconductor device comprising a logic cell that is on a substrate and includes first and second active regions spaced apart from each other in a first direction, first and second active patterns that are respectively on the first and second active regions and extend in a second direction intersecting the first direction, gate electrodes extending in the first direction and running across the first and second active patterns, first connection lines that are in a first interlayer dielectric layer on the gate electrodes and extend parallel to each other in the second direction, and second connection lines that are in a second interlayer dielectric layer on the first interlayer dielectric layer and extend parallel to each other in the first direction.

Embodiments of the present application provide a semiconductor structure and a formation method thereof. The semiconductor structure formation method includes: providing a substrate, a dielectric layer on the substrate, the dielectric layer having a trench; forming a metallic copper layer filling the trench; forming a contact layer on an upper surface of the metallic copper layer, a material of the contact layer containing cuprous ions; and forming a barrier layer on an upper surface of the contact layer, a material of the barrier layer containing a same element as the material of the contact layer. The embodiments of the present application help improve a contact effect between the metallic copper layer and the barrier layer.

Embodiments herein include void-free material depositions on a substrate (e.g., in a void-free trench-filled (VFTF) component). In some embodiments, a method may include providing a plurality of device structures extending from a base, each of the plurality of device structures including a first sidewall opposite a second sidewall and a top surface extending between the first and second sidewalls, and providing a seed layer over the plurality of device structures. The method may further include forming a dielectric layer along just the top surface and along an upper portion of the first and second sidewalls using an angled deposition delivered to the plurality of device structures at a non-zero angle of inclination relative to a perpendicular extending from an upper surface of the base, and forming a fill material within one or more trenches defined by the plurality of device structures.

Embodiments of the present disclosure provide a patterning method and a semiconductor structure. The method includes: providing a substrate, wherein the substrate includes adjacent storage regions and peripheral circuit regions; forming, on the substrate, a pattern transfer layer, the pattern transfer layer having a plurality of first hard masks, wherein the first hard masks extend along a first direction and are spaced apart from each other; forming a barrier layer on the pattern transfer layer; forming, on the barrier layer, a plurality of second hard masks, the plurality of second hard masks extending along a second direction, wherein the second hard masks are spaced apart from each other, and the second hard masks are located in the storage regions and second hard masks close to the peripheral circuit regions have structural defects.

A method of manufacturing a dynamic random access memory is provided and includes: forming a hard mask layer on a substrate; forming an opening in the hard mask layer and the substrate; forming a dielectric layer on a sidewall of the opening; forming a first part of a buried word line in a lower part of the opening; forming a hard mask layer on a top surface of the hindering layer, where the hindering layer has overhangs covering top corners of the hard mask layer; depositing a first barrier layer on the substrate through hindrance of the overhangs, where the first barrier layer covers the hindering layer and a top surface of the first part and exposes the dielectric layer on the sidewall of the opening; and forming a first conductive layer in the opening, where a sidewall of the first conductive layer contacts the dielectric layer.

A semiconductor structure for a DRAM is described having multiple layers of arrays of thyristor memory cells with silicon-germanium base regions. Memory cells in a vertical string extending through the layers have an electrical connection to one terminal of the memory cells in that string. Word lines couple the strings together. Each layer of the array also includes bit line connections to memory cells on that layer. Select transistors enable the use of folded bit lines. Methods of fabricating the array are described.