Provided is a memory structure including first and second transistors, an isolation structure, a conductive layer and a capacitor. Each of the first and second transistors includes a gate disposed on the substrate and source/drain regions disposed in the substrate. The isolation structure is disposed in the substrate between the first and second transistors. The conductive layer is disposed above the first and second transistors and includes a circuit portion electrically connected to the first and second transistors and a dummy portion located above the isolation structure. The capacitor is disposed between the first and second transistors. The capacitor includes a body portion and first and second extension portions. The first and second extension portions extend from the body portion to the source/drain regions of the first and the second transistors, respectively. The first and second extension portions are disposed between the circuit portion and the dummy portion, respectively.

Isolation between vertical thyristor memory cells in an array is improved with isolation regions between the vertical thyristor memory cells. The isolation regions are formed by electrically isolating cores surrounded by insulating material, such as silicon dioxide, in trenches between the memory cells. The electrically isolating cores may be tubes of air or conducting rods. Methods of constructing the isolation regions in a processes for manufacturing vertical thyristor memory cell arrays are also disclosed.

A semiconductor memory device includes a plurality of memory cell transistors arranged along a common semiconductor layer. Each of the plurality of memory cell transistors comprises a first source/drain region and a second source/drain region formed in the common semiconductor layer; a gate stack formed on a portion of the common semiconductor layer between the first source/drain region and the second source/drain region; and an electrical floating portion in the portion of the common semiconductor layer, a charge state of the electrical floating portion being adapted to adjust a threshold voltage and a channel conductance of the memory cell transistor. The plurality of memory cell transistors connected in series with each other along the common semiconductor layer provide a memory string.

Some embodiments include apparatuses and methods of forming the apparatuses. One of the apparatuses includes a memory cell and first, second, and third data lines located over a substrate. The memory cell includes a first transistor and a second transistor. The first transistor includes a charge storage structure located on a first level of the apparatus, and a first channel region electrically separated from the charge storage structure. The second transistor includes a second channel region located on a second level of the apparatus and electrically coupled to the charge storage structure. The first and second data lines are located on a third level of the apparatus and electrically coupled to the first channel region. The first level is between the substrate and the third level. The third data line is electrically coupled to the second channel region and electrically separated from the first channel region.

With the disclosed systems and methods for DRAM and 3D NAND inspection, an image of the wafer is received based on the output for an inspection tool. Geometric measurements of a design of a plurality of memory devices on the wafer are received. A care area with higher inspection sensitivity is determined based on the geometric measurements.

A method of manufacturing a semiconductor device includes: forming a lower structure that includes a substrate and conductive lines on the substrate, within a chip region and an edge region of the lower structure; forming data storage structures on the chip region of the lower structure; forming dummy structures on the edge region of the lower structure; forming an interlayer insulating layer covering the data storage structures and the dummy structures on the lower structure, the interlayer insulating layer including high step portions and low step portions, an upper end of the low step portions being lower than an upper end of the high step portions; and planarizing the interlayer insulating layer.

Provided are a semiconductor structure and a method for preparing the same. The method for preparing a semiconductor structure includes: a substrate is provided; a stacked structure is formed on the substrate; a first capacitor having a first bottom electrode, a first dielectric layer and a first top electrode is formed in the stacked structure, in which the first bottom electrode is of a columnar structure; and a second capacitor having a second bottom electrode, a second dielectric layer and a second top electrode is formed on the first capacitor, in which the second bottom electrode is of a concave structure. The second dielectric layer is formed between the second bottom electrode and the second top electrode, and the second dielectric layer is further formed between the second bottom electrodes of adjacent second capacitors.

A semiconductor device, a preparation method thereof and a memory apparatus are provided. The semiconductor device includes a semiconductor substrate on which multiple strip-shaped stacked structures and a sidewall structure covering a periphery of each stacked structure are disposed, and a conductive structure is disposed on a side of the stacked structure far away from the semiconductor substrate. The stacked structure includes a conductor layer disposed on the semiconductor substrate and configured to transmit a data signal, an isolation layer disposed on a side of the conductor layer far away from the semiconductor substrate, a separation layer disposed on a side of the isolation layer far away from the semiconductor substrate and made of a low dielectric constant material, and a dielectric layer disposed on a side of the separation layer far away from the semiconductor substrate and configured to isolate the separation layer from the conductive structure.

The present disclosure relates to a semiconductor device including a conductive contact having a tapering profile and a method for preparing the semiconductor device. The semiconductor device includes a conductive layer disposed over a semiconductor substrate, and a conductive contact disposed over the conductive layer. The semiconductor device also includes a conductive line disposed over the conductive contact. An upper portion of the conductive contact has a tapering profile in a first cross-sectional view along a longitudinal axis of the conductive line, and the upper portion of the conductive contact has a non-tapering profile in a second cross-sectional view along a line orthogonal to the longitudinal axis of the conductive line.

A semiconductor structure manufacturing method includes: providing a substrate; forming a first insulating layer covering the substrate, and patterning the first insulating layer to form a plurality of vias and a plurality of isolation structures that are alternatingly distributed; forming conductive contact plugs in the vias respectively, where the conductive contact plugs cover bottoms of the vias and each includes a first region and a second region adjacent to each other, and the conductive contact plugs located in the first regions cover outer walls of the isolation structures and extend along the outer walls to surfaces of the isolation structures distal from the substrate; and forming a passivation layer covering side walls and surfaces of the conductive contact plugs.