Three-dimensional dynamic random-access memory (3D DRAM) structures and methods of formation of same are provided herein. In some embodiments, a 3D DRAM stack can include alternating silicon (Si) layers and silicon germanium (SiGe) layers. Each of the Si layers may have a height greater than a height of each of the SiGe layers. Methods and systems for formation of such structures are further provided.

A semiconductor structure includes: a substrate, a first gate structure, and a second gate structure. The substrate includes: discrete first semiconductor pillars arranged at a top of the substrate and extending in a vertical direction; and a second semiconductor pillar and a third semiconductor pillar extending in the vertical direction, the second and third semiconductor pillars are provided at a top of each first semiconductor pillar. The first gate structure is arranged in a middle region of the first semiconductor pillar and surrounds the first semiconductor pillar. The second gate structure is arranged in a middle region of the second semiconductor pillar and of the third semiconductor pillar, and includes a first ring structure and a second ring structure. The first ring structure surrounds the second semiconductor pillar, and the second ring structure surrounds the third semiconductor pillar.

The present application provides a method for manufacturing a semiconductor structure, a semiconductor structure, and a memory. The method for manufacturing a semiconductor structure includes the following steps: providing a substrate, and forming a stabilizing layer on the substrate; forming a stabilizing structure consisting of a plurality of linear structures and grooves among the linear structures; forming a hard mask layer covering the stabilizing structure; forming a mask pattern connected to a top of the linear structure and an inner wall of the groove on the hard mask layer; and transferring the mask pattern to the substrate.

A method for manufacturing a semiconductor device includes providing a semiconductor substrate including a first and second regions; forming a first dielectric layer on the semiconductor substrate; forming a temporary layer on the first dielectric layer; performing a first heat treatment process on the first dielectric layer and the temporary layer; removing the temporary layer to expose the first dielectric layer; and performing a second heat treatment process on the first dielectric layer.

A memory and a method for preparing a memory are provided. The method for preparing the memory includes: providing a substrate, in which the substrate includes a first N-type active region and a first P-type active region; forming an epitaxial layer covering the first P-type active region, in which the epitaxial layer exposes the first N-type active region; simultaneously forming a first gate dielectric layer covering the first N-type active region and a second gate dielectric layer covering the epitaxial layer, in which a thickness of the first gate dielectric layer is substantially the same as a thickness of the second gate dielectric layer; forming a first gate covering the first gate dielectric layer to form a first N-channel Metal Oxide Semiconductor (NMOS) device; and forming a second gate covering the second gate dielectric layer to form a first P-channel Metal Oxide Semiconductor (PMOS) device.

Provided are a shallow trench isolation structure and a method for manufacturing the same. The shallow trench isolation structure includes a substrate, a first isolation structure, a second isolation structure and a third isolation structure. The substrate includes a first trench. The first isolation layer is located in the first trench and provided with a second trench. The second isolation layer is located in the second trench and provided with a third trench. The third isolation layer fills the third trench. The second trench is a V-shaped trench, and a bottom surface of the second isolation layer is a V-shaped surface that is adapted to a shape of the second trench.

A semiconductor structure for a DRAM is described having multiple layers of arrays of memory cells. Memory cells in a vertical string extending through the layers have an electrical connection to one terminal of the memory cells in that string. Word lines couple the strings together. Each layer of the array also includes bit line connections to memory cells on that layer. Select transistors enable the use of folded bit lines. The memory cells preferably are thyristors. Methods of fabricating the array are described.

Provided is a step of forming, on a P-layer substrate 20, an N.sup.+ layer 21A to be connected to a source line SL, Si pillars 25a to 25d, N.sup.+ layers 23A to 23D to be connected to bit lines BL1 and BL2, HfO.sub.2 layers 30a and 32 surrounding lower and upper portions of the Si pillars 25a to 25d, a TiN layer 31a to be connected to a plate line PL, and TiN layers 33a and 33b to be connected to word lines WL1 and WL2. P layers 27a to 27d are formed so as to surround the Si pillars 25a to 25d and so as to be deposited on them to form a plurality of dynamic flash memory cells arranged in rows and columns.

A method may include forming in a substrate a first array of a first material of first linear structures, interspersed with a second array of a second material, of second linear structures, the first and second linear structures elongated along a first axis. The method may include generating a chop pattern in the first layer, comprising a third linear array, interspersed with a fourth linear array. The third and fourth linear arrays may be elongated along a second axis, forming a non-zero angle of incidence with respect to the first axis. The third linear array may include alternating portions of the first and second material, while the fourth linear array comprises an array of cavities, arranged within the patterning layer. The method may include elongating a first set of cavities along the first axis, to form a first set of elongated cavities bounded by the first material.

A novel semiconductor device is provided. A structure body extending in a first direction, a first conductor extending in a second direction, and a second conductor extending in the second direction are provided. In a first intersection portion where the structure body and the first conductor intersect with each other, a first insulator, a first semiconductor, a second insulator, a second semiconductor, a third insulator, a fourth insulator, and a fifth insulator are provided concentrically around a third conductor. In a second intersection portion where the structure body and the second conductor intersect with each other, the first insulator, the first semiconductor, the second insulator, a fourth conductor, the second semiconductor, and the third insulator are provided concentrically around the third conductor.