A semiconductor device includes a bit line extending in a first direction, a gate electrode extending in a second direction, and a semiconductor pattern extending in a third direction and connected to the bit line, and a capacitor. The capacitor includes a first electrode connected to the semiconductor pattern and a dielectric film between the first and second electrodes. The first or the second direction is perpendicular to an upper surface of the substrate. The first electrode includes an upper and a lower plate region parallel to the upper surface of the substrate, and a connecting region which connects the upper and the lower plate regions. The upper and the lower plate regions of the first electrode include an upper and a lower surface facing each other. The dielectric film extends along the upper and the lower surfaces of the upper and lower plate regions of the first electrode.

The present disclosure provides a semiconductor structure. The semiconductor structure comprises a substrate having a first top surface. An active region is surrounded by an isolation region in the substrate. A buried power line and a buried signal line are disposed within the substrate and in the active region. A first circuit layer is disposed on the first top surface of the substrate to cover the buried power line and the buried signal line. A second circuit layer is disposed on the first top surface of the substrate and separated from the first circuit layer. A cell capacitor is disposed on and electrically coupled to the first circuit layer.

A semiconductor device, the device including: a plurality of transistors, where at least one of the plurality of transistors includes a first single crystal source, channel, and drain, where at least one of the plurality of transistors includes a second single crystal source, channel, and drain, where the second single crystal source, channel, and drain is disposed above the first single crystal source, channel, and drain, where at least one of the plurality of transistors includes a third single crystal source, channel, and drain, where the third single crystal source, channel, and drain is disposed above the second single crystal source, channel, and drain, where at least one of the plurality of transistors includes a fourth single crystal source, channel, and drain, and where the first single crystal source or drain, and the second single crystal source or drain each include n+ doped regions.

A 3D semiconductor device, the device including: a first level including a first single crystal layer, the first level including first transistors, where the first transistors each include a single crystal channel; first metal layers interconnecting at least the first transistors; and a second level including a second single crystal layer, the second level including second transistors, where the second level overlays the first level, where the second level is bonded to the first level, where the bonded includes oxide to oxide bonds, where the second transistors each include at least two side-gates, and where through the first metal layers power is provided to at least one of the second transistors.

On a substrate, a first semiconductor layer 1 is formed; from a portion of the layer 1, a first impurity layer 3 extends vertically, and a second semiconductor layer 4 is disposed on the layer 3; side walls of the layers 3 and 4 and the layer 1 are covered with a first gate insulating layer 2; in the resultant grooves, a first gate conductor layer 22 and a second insulating layer 6 are disposed; over the second semiconductor layer 4, layers are disposed that are a third semiconductor layer 8, an n+ layer 7a connecting to a source line SL and an n+ layer 7b connecting to a bit line BL that are disposed on both sides of the layer 8, a second gate insulating layer 9 formed so as to cover the layer 8, and a second gate conductor layer 10 connecting to a word line WL.

A semiconductor memory instance is provided that includes an array of memory cells. The array includes a plurality of semiconductor memory cells arranged in at least one column and at least one row. Each of the semiconductor memory cells includes a floating body region configured to be charged to a level indicative of a state of the memory cell. Further includes are a plurality of buried well regions, wherein each of the buried well regions can be individually selected, and a decoder circuit to select at least one of the buried well regions.

A p layer is a semiconductor base material. An n+ layer is disposed on one extension side of the layer. An n+ layer is disposed on the opposite side in contact with the layer. A gate insulating layer partially covers the layers. A gate conductor layer is disposed in contact with the layer. A gate insulating layer partially covers the layers. A gate conductor layer is disposed in electrical separation from the layer. Memory operation is performed by applying voltage to each of the layers. In this case, the gate capacitance of a MOS structure constituted by the layers per unit area is smaller than that of a MOS structure constituted by the layers.

A transistor comprises a top source/drain region, a bottom source/drain region, a channel region vertically between the top and bottom source/drain regions, and a gate operatively laterally-adjacent the channel region. At least one of the top source/drain region, the bottom source/drain region, and the channel region are crystalline. All crystal grains within the at least one of the top source/drain region, the bottom source/drain region, and the channel region have average crystal sizes within 0.064 μm.sup.3 of one another. Other embodiments, including methods, are disclosed.

A method for producing a 3D semiconductor device including: providing a first level including a first single crystal layer; forming a first metal layer on top of the first level; forming a second metal layer on top of the first metal layer; forming at least one second level above the second metal layer; performing a first lithography step on the second level; forming a third level on top of the second level; performing processing steps to form first memory cells within the second level and form second memory cells within the third level, where the first memory cells include at least one second transistor, and the second memory cells include at least one third transistor; and then at performing at least one deposition step which deposits gate electrodes for both the second and the third transistors, and forming at least four independent memory arrays.

On a substrate Sub, a semiconductor base material (Si pillar) that stands on the substrate in a vertical direction or that extends along the substrate in a horizontal direction a first impurity layer and a second impurity layer that are disposed on respective ends of the semiconductor base material, a first gate conductor layer, and a second gate conductor layer that surround the semiconductor base material between the first impurity layer and the second impurity layer, and a channel semiconductor layer are disposed. Voltages are applied to perform a memory write operation of discharging a group of electrons from the channel semiconductor layer and retaining some of a group of positive holes in the channel semiconductor layer generated inside the channel semiconductor layer by a gate-induced drain leakage current, and a memory erase operation of discharging the group of positive holes retained in the channel semiconductor layer.